diff mbox series

[v2,4/5] arm64: dts: mt8186: Add dsi node

Message ID 20221123135531.23221-5-allen-kh.cheng@mediatek.com
State New
Headers
Series Add some driver nodes for MT8186 SoC |

Commit Message

Allen-KH Cheng Nov. 23, 2022, 1:55 p.m. UTC 
  Add dsi node for mt8186 SoC.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Matthias Brugger Nov. 23, 2022, 3:30 p.m. UTC | #1 
On 23/11/2022 14:55, Allen-KH Cheng wrote:
> Add dsi node for mt8186 SoC.
> 
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index c0481f0dc527..4a2f7ad3c6f0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -979,6 +979,25 @@
>   			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
>   		};
>   
> +		dsi0: dsi@14013000 {
> +			compatible = "mediatek,mt8186-dsi";
> +			reg = <0 0x14013000 0 0x1000>;
> +			clocks = <&mmsys CLK_MM_DSI0>,
> +				 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
> +				 <&mipi_tx0>;
> +			clock-names = "engine", "digital", "hs";
> +			interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
> +			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> +			resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
> +			phys = <&mipi_tx0>;
> +			phy-names = "dphy";
> +			status = "disabled";
> +
> +			port {
> +				dsi_out: endpoint { };
> +			};
> +		};
> +
>   		iommu_mm: iommu@14016000 {
>   			compatible = "mediatek,mt8186-iommu-mm";
>   			reg = <0 0x14016000 0 0x1000>;
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index c0481f0dc527..4a2f7ad3c6f0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -979,6 +979,25 @@ 
 			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
 		};
 
+		dsi0: dsi@14013000 {
+			compatible = "mediatek,mt8186-dsi";
+			reg = <0 0x14013000 0 0x1000>;
+			clocks = <&mmsys CLK_MM_DSI0>,
+				 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
+			resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			status = "disabled";
+
+			port {
+				dsi_out: endpoint { };
+			};
+		};
+
 		iommu_mm: iommu@14016000 {
 			compatible = "mediatek,mt8186-iommu-mm";
 			reg = <0 0x14016000 0 0x1000>;