| Message ID | 20240204090336.3209063-1-s-vadapalli@ti.com |
|---|---|
| State | New |
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From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <lee@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>
CC: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
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Subject: [PATCH v2] dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl
compatible
Date: Sun, 4 Feb 2024 14:33:36 +0530
Message-ID: <20240204090336.3209063-1-s-vadapalli@ti.com>
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| Series |
[v2] dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible
|
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Commit Message
Siddharth Vadapalli
Feb. 4, 2024, 9:03 a.m. UTC
The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC
are used to configure the link speed, lane count and mode of operation
of the respective PCIe instance. Add compatible for allowing the PCIe
driver to obtain a regmap for the PCIE_CTRL register within the System
Controller device-tree node in order to configure the PCIe instance
accordingly.
The Technical Reference Manual for J784S4 SoC with details of the
PCIE_CTRL registers is available at: https://www.ti.com/lit/zip/spruj52
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on linux-next tagged next-20240202.
v1:
https://lore.kernel.org/r/20240131112342.1300893-1-s-vadapalli@ti.com/
Changes since v1:
- Changed compatible to be SoC specific.
- Updated commit message to be SoC specific.
Regards,
Siddharth.
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
Comments
On 04/02/2024 10:03, Siddharth Vadapalli wrote: > The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC > are used to configure the link speed, lane count and mode of operation > of the respective PCIe instance. Add compatible for allowing the PCIe > driver to obtain a regmap for the PCIE_CTRL register within the System > Controller device-tree node in order to configure the PCIe instance > accordingly. > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Sun, 04 Feb 2024 14:33:36 +0530, Siddharth Vadapalli wrote: > The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC > are used to configure the link speed, lane count and mode of operation > of the respective PCIe instance. Add compatible for allowing the PCIe > driver to obtain a regmap for the PCIE_CTRL register within the System > Controller device-tree node in order to configure the PCIe instance > accordingly. > > [...] Applied, thanks! [1/1] dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible commit: 90ba55d8e3bce146a7368d271cea1b7a1d0643bb -- Lee Jones [李琼斯]
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 084b5c2a2a3c..2376b612f94e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -73,6 +73,7 @@ properties: - rockchip,rv1126-qos - starfive,jh7100-sysmain - ti,am654-dss-oldi-io-ctrl + - ti,j784s4-pcie-ctrl - const: syscon