Message ID | 20231212033259.189718-2-aford173@gmail.com |
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State | New |
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Mon, 11 Dec 2023 19:33:15 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:6068:4690:ab38:4373]) by smtp.gmail.com with ESMTPSA id y23-20020a5e8717000000b007b457153a6bsm2590049ioj.28.2023.12.11.19.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 19:33:15 -0800 (PST) From: Adam Ford <aford173@gmail.com> To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford <aford173@gmail.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Inki Dae <inki.dae@samsung.com>, Jagan Teki <jagan@amarulasolutions.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Michael Tretter <m.tretter@pengutronix.de>, Marco Felsch <m.felsch@pengutronix.de>, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/bridge: samsung-dsim: Fix porch calcalcuation rounding Date: Mon, 11 Dec 2023 21:32:59 -0600 Message-Id: <20231212033259.189718-2-aford173@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231212033259.189718-1-aford173@gmail.com> References: <20231212033259.189718-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); 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[1/2] drm/bridge: samsung-dsim: Set P divider based on min/max of fin pll
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Commit Message
Adam Ford
Dec. 12, 2023, 3:32 a.m. UTC
When using video sync pulses, the HFP, HBP, and HSA are divided between the available lanes if there is more than one lane. For certain timings and lane configurations, the HFP may not be evenly divisible. If the HFP is rounded down, it ends up being too small which can cause some monitors to not sync properly. In these instances, adjust htotal and hsync to round the HFP up, and recalculate the htotal. Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor Signed-off-by: Adam Ford <aford173@gmail.com>
Comments
On Mon, Dec 11, 2023 at 9:33 PM Adam Ford <aford173@gmail.com> wrote: > > When using video sync pulses, the HFP, HBP, and HSA are divided between > the available lanes if there is more than one lane. For certain > timings and lane configurations, the HFP may not be evenly divisible. > If the HFP is rounded down, it ends up being too small which can cause > some monitors to not sync properly. In these instances, adjust htotal > and hsync to round the HFP up, and recalculate the htotal. > For anyone who's following this, I added a note which I apparently forgot to save: This adds support for 720p60 in the i.MX8M Plus. NXP uses a look-up table in their downstream code to accomplish this. Using this calculation, the driver can adjust without the need for a complicated table and should be flexible for different timings and resolutions depending on the monitor. I don't have a DSI analyzer, and this appears to only work on i.MX8M Plus but not Mini and Nano for some reason, despite their having a similar DSI bridge. When Frieder teste this, he reported no changes on the Kontrol BL i.MX8MM: "So at least there is no negative impact in this case" If someone else has an i.MX8MP, I would appreciate any feedback. thanks adam > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index 239d253a7d71..f5795da1d8bb 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -1628,6 +1628,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, > adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); > } > > + /* > + * When using video sync pulses, the HFP, HBP, and HSA are divided between > + * the available lanes if there is more than one lane. For certain > + * timings and lane configurations, the HFP may not be evenly divisible. > + * If the HFP is rounded down, it ends up being too small which can cause > + * some monitors to not sync properly. In these instances, adjust htotal > + * and hsync to round the HFP up, and recalculate the htotal. Through trial > + * and error, it appears that the HBP and HSA do not appearto need the same > + * correction that HFP does. > + */ > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) { > + int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; > + int remainder = hfp % dsi->lanes; > + > + if (remainder) { > + adjusted_mode->hsync_start += remainder; > + adjusted_mode->hsync_end += remainder; > + adjusted_mode->htotal += remainder; > + } > + } > + > return 0; > } > > -- > 2.40.1 >
On Mon, Dec 11, 2023 at 9:33 PM Adam Ford <aford173@gmail.com> wrote: > > When using video sync pulses, the HFP, HBP, and HSA are divided between > the available lanes if there is more than one lane. For certain > timings and lane configurations, the HFP may not be evenly divisible. > If the HFP is rounded down, it ends up being too small which can cause > some monitors to not sync properly. In these instances, adjust htotal > and hsync to round the HFP up, and recalculate the htotal. > > Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor > Signed-off-by: Adam Ford <aford173@gmail.com> Gentle nudge on this one. Basically this fixes an issue with the 8MP, but it's still unknown why it doesn't work on 8MM or 8MN, but Frieder confirmed there are no regressions on 8MM or 8MN. adam > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index 239d253a7d71..f5795da1d8bb 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -1628,6 +1628,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, > adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); > } > > + /* > + * When using video sync pulses, the HFP, HBP, and HSA are divided between > + * the available lanes if there is more than one lane. For certain > + * timings and lane configurations, the HFP may not be evenly divisible. > + * If the HFP is rounded down, it ends up being too small which can cause > + * some monitors to not sync properly. In these instances, adjust htotal > + * and hsync to round the HFP up, and recalculate the htotal. Through trial > + * and error, it appears that the HBP and HSA do not appearto need the same > + * correction that HFP does. > + */ > + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) { > + int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; > + int remainder = hfp % dsi->lanes; > + > + if (remainder) { > + adjusted_mode->hsync_start += remainder; > + adjusted_mode->hsync_end += remainder; > + adjusted_mode->htotal += remainder; > + } > + } > + > return 0; > } > > -- > 2.40.1 >
On 25.01.24 19:44, Adam Ford wrote: > On Mon, Dec 11, 2023 at 9:33 PM Adam Ford <aford173@gmail.com> wrote: >> >> When using video sync pulses, the HFP, HBP, and HSA are divided between >> the available lanes if there is more than one lane. For certain >> timings and lane configurations, the HFP may not be evenly divisible. >> If the HFP is rounded down, it ends up being too small which can cause >> some monitors to not sync properly. In these instances, adjust htotal >> and hsync to round the HFP up, and recalculate the htotal. >> >> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor >> Signed-off-by: Adam Ford <aford173@gmail.com> > > Gentle nudge on this one. Basically this fixes an issue with the 8MP, > but it's still unknown why it doesn't work on 8MM or 8MN, but Frieder > confirmed there are no regressions on 8MM or 8MN. I only tested two specific display setups on i.MX8MM. So of course I can't confirm the absence of regressions in general. Anyway, I think this should be applied.
On Mon, Jan 29, 2024 at 2:17 AM Frieder Schrempf <frieder.schrempf@kontron.de> wrote: > > On 25.01.24 19:44, Adam Ford wrote: > > On Mon, Dec 11, 2023 at 9:33 PM Adam Ford <aford173@gmail.com> wrote: > >> > >> When using video sync pulses, the HFP, HBP, and HSA are divided between > >> the available lanes if there is more than one lane. For certain > >> timings and lane configurations, the HFP may not be evenly divisible. > >> If the HFP is rounded down, it ends up being too small which can cause > >> some monitors to not sync properly. In these instances, adjust htotal > >> and hsync to round the HFP up, and recalculate the htotal. > >> > >> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor > >> Signed-off-by: Adam Ford <aford173@gmail.com> > > > > Gentle nudge on this one. Basically this fixes an issue with the 8MP, > > but it's still unknown why it doesn't work on 8MM or 8MN, but Frieder > > confirmed there are no regressions on 8MM or 8MN. > Inki, Is there something you need which is holding this back? It's been nearly two months since I posted the initial patch. Thank you, adam > I only tested two specific display setups on i.MX8MM. So of course I > can't confirm the absence of regressions in general. > > Anyway, I think this should be applied.
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 239d253a7d71..f5795da1d8bb 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1628,6 +1628,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); } + /* + * When using video sync pulses, the HFP, HBP, and HSA are divided between + * the available lanes if there is more than one lane. For certain + * timings and lane configurations, the HFP may not be evenly divisible. + * If the HFP is rounded down, it ends up being too small which can cause + * some monitors to not sync properly. In these instances, adjust htotal + * and hsync to round the HFP up, and recalculate the htotal. Through trial + * and error, it appears that the HBP and HSA do not appearto need the same + * correction that HFP does. + */ + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) { + int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; + int remainder = hfp % dsi->lanes; + + if (remainder) { + adjusted_mode->hsync_start += remainder; + adjusted_mode->hsync_end += remainder; + adjusted_mode->htotal += remainder; + } + } + return 0; }