LoongArch: Split vec_selects of bottom elements into simple move
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Commit Message
For below pattern, can be treated as a simple move because floating point
and vector share a common register on loongarch64.
(set (reg/v:SF 32 $f0 [orig:93 res ] [93])
(vec_select:SF (reg:V8SF 32 $f0 [115])
(parallel [
(const_int 0 [0])
])))
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_extract<mode>_0):
New define_insn_and_split patten.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vect-extract.c: New test.
Comments
Pushed to r14-8447.
在 2024/1/16 上午10:23, Jiahao Xu 写道:
> For below pattern, can be treated as a simple move because floating point
> and vector share a common register on loongarch64.
>
> (set (reg/v:SF 32 $f0 [orig:93 res ] [93])
> (vec_select:SF (reg:V8SF 32 $f0 [115])
> (parallel [
> (const_int 0 [0])
> ])))
>
> gcc/ChangeLog:
>
> * config/loongarch/lasx.md (vec_extract<mode>_0):
> New define_insn_and_split patten.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/loongarch/vect-extract.c: New test.
>
> diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
> index 72f7161311c..90f66ee4d24 100644
> --- a/gcc/config/loongarch/lasx.md
> +++ b/gcc/config/loongarch/lasx.md
> @@ -761,6 +761,21 @@ (define_expand "vec_extract<mode><unitmode>"
> DONE;
> })
>
> +(define_insn_and_split "vec_extract<mode>_0"
> + [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
> + (vec_select:<UNITMODE>
> + (match_operand:FLASX 1 "register_operand" "f")
> + (parallel [(const_int 0)])))]
> + "ISA_HAS_LSX"
> + "#"
> + "&& reload_completed"
> + [(set (match_dup 0) (match_dup 1))]
> +{
> + operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
> +}
> + [(set_attr "move_type" "fmove")
> + (set_attr "mode" "<UNITMODE>")])
> +
> (define_expand "vec_perm<mode>"
> [(match_operand:LASX 0 "register_operand")
> (match_operand:LASX 1 "register_operand")
> diff --git a/gcc/testsuite/gcc.target/loongarch/vect-extract.c b/gcc/testsuite/gcc.target/loongarch/vect-extract.c
> new file mode 100644
> index 00000000000..ce126e3a4f1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/vect-extract.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -ffast-math -mlasx -fno-vect-cost-model -fno-unroll-loops" } */
> +/* { dg-final { scan-assembler-not "xvpickve.w" } } */
> +/* { dg-final { scan-assembler-not "xvpickve.d" } } */
> +
> +float
> +sum_float (float *a, int n) {
> + float res = 0.0;
> + for (int i = 0; i < n; i++)
> + res += a[i];
> + return res;
> +}
> +
> +double
> +sum_double (double *a, int n) {
> + double res = 0.0;
> + for (int i = 0; i < n; i++)
> + res += a[i];
> + return res;
> +}
@@ -761,6 +761,21 @@ (define_expand "vec_extract<mode><unitmode>"
DONE;
})
+(define_insn_and_split "vec_extract<mode>_0"
+ [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
+ (vec_select:<UNITMODE>
+ (match_operand:FLASX 1 "register_operand" "f")
+ (parallel [(const_int 0)])))]
+ "ISA_HAS_LSX"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+{
+ operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
+}
+ [(set_attr "move_type" "fmove")
+ (set_attr "mode" "<UNITMODE>")])
+
(define_expand "vec_perm<mode>"
[(match_operand:LASX 0 "register_operand")
(match_operand:LASX 1 "register_operand")
new file mode 100644
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mlasx -fno-vect-cost-model -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-not "xvpickve.w" } } */
+/* { dg-final { scan-assembler-not "xvpickve.d" } } */
+
+float
+sum_float (float *a, int n) {
+ float res = 0.0;
+ for (int i = 0; i < n; i++)
+ res += a[i];
+ return res;
+}
+
+double
+sum_double (double *a, int n) {
+ double res = 0.0;
+ for (int i = 0; i < n; i++)
+ res += a[i];
+ return res;
+}