Message ID | 20240116094935.9988-3-quic_riteshk@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:42cf:b0:101:a8e8:374 with SMTP id q15csp148741dye; Tue, 16 Jan 2024 01:51:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPoG/TVz0Rl0vnOO1LScy7lyiNWEB/w3S5RpiWc6l30ED2sHLfFyv+LEnx4V/CcKLqUGXn X-Received: by 2002:a17:906:f84b:b0:a2e:51ab:8a2f with SMTP id ks11-20020a170906f84b00b00a2e51ab8a2fmr1061576ejb.73.1705398671407; Tue, 16 Jan 2024 01:51:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705398671; cv=none; d=google.com; s=arc-20160816; b=N0VBiFDHlMb+Qlkms53RfZPJamljFL9DWICEniOhvNfp0urFhHQRjj0fFk2zO8JH/U TFT+YnknnmkHjnanmWDeIpUrqCbcwD/lCvetyvQ2IkdJsN7rYfR69oksZ4nSPsTzvbtN YBbUJF10xgxSao79TvitKe9pzLvafOpKRuJITJSO35rxyKlBsUGsP10uIMOU2+0X1DLj OUMl7DQt4Iy5j3PEy38d0+xAivE35kYcBMjjtBjZDPFTzkMmeq4Wx5JLzN0EE3kQ5sNc +MMcPZlqoAE5vHDP9dmwBxPtpIKIvT8uIF3NTmnXoOd9Tn6t50clhkCrpuOirMW7V7yh F4Mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=wQAX+VhAFdlMCGP8X0aXUlSO5dSynGBqLOMB5EIi+c0=; fh=WZstEXrC2jNs8p3PSpHSsjyFV5KU9tdEQ7/SGaoa91s=; b=H4O1jOjEZEDw0lh34PI/tE7gmekdu1RNU5z2dZS7kzHcRmHHREyY7ePUMQYRkhKpuS cWwlJyDpaMxfk3lX0bwvd4SrGAL8A2frpg4maHkNEgGOzTATvSzLnVoMVFgpBIv0vqZ7 1NYuO+Ed/+IDpsc19jrdQcG2nWkOb3cFB8Rpzeu51KD4ZyALcCw38SCc3wkqa40ZqBmB Nv/sonXR9YkzOfLfx6DsfseNqjeg0w/XfKchC7GjvidsGwV2r//E5wHibhyur3l4Jdtg bfQbb72mGE5Eteo0uEUeDIuvm5iP1AX9OszSEhGm03shtaA9W9dim2IKuqynlCBi1/8m uliA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IzVl8V+8; spf=pass (google.com: domain of linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id w26-20020a1709060a1a00b00a275b4b24dfsi4416884ejf.789.2024.01.16.01.51.11 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 01:51:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IzVl8V+8; spf=pass (google.com: domain of linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-27204-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id DE7461F2327F for <ouuuleilei@gmail.com>; Tue, 16 Jan 2024 09:51:08 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 15F021756C; Tue, 16 Jan 2024 09:50:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IzVl8V+8" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04170125BC; Tue, 16 Jan 2024 09:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40G7xBZW006658; Tue, 16 Jan 2024 09:49:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= qcppdkim1; bh=wQAX+VhAFdlMCGP8X0aXUlSO5dSynGBqLOMB5EIi+c0=; b=Iz Vl8V+8rellap5+ZCBBWVu4RT5fxmQ5cybHN0TztDyoyQi7Q6yk+U/IOhSOQc4Uf3 5BEDzGGkfJRWz9AN3XTa5Li7JbyVYD+eEJlMY3H/02uW9vi08yDKY3WUUQJTV5N6 rI/HPqwDgl07dpr/bwlbrM2yOfZ8VGy8FM7l8Ks/FA0I4ICkpXAoJjlJplxSgIiW s4CGLVn0u7cUUHXXuvlDbiq2evMa5xPOinbSEAb7RpY4lHtEjmyAcamKLTTZmDg0 5QpXoIRY6sQCekkOfZt3SRp1db0UJlRotHuZn1muDLWdsKXBbGBtSsoW2EJjg1+a A6q7vqea6N35wuZG/BGg== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vnnvbg6wc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 16 Jan 2024 09:49:45 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 40G9nfs0006270; Tue, 16 Jan 2024 09:49:41 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3vkkkkmgev-1; Tue, 16 Jan 2024 09:49:41 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40G9nfIj006250; Tue, 16 Jan 2024 09:49:41 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-riteshk-hyd.qualcomm.com [10.147.241.247]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 40G9neYq006247; Tue, 16 Jan 2024 09:49:41 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2314801) id A6ADB601957; Tue, 16 Jan 2024 15:19:39 +0530 (+0530) From: Ritesh Kumar <quic_riteshk@quicinc.com> To: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, arnd@arndb.de, neil.armstrong@linaro.org, dmitry.baryshkov@linaro.org, nfraprado@collabora.com, m.szyprowski@samsung.com Cc: Ritesh Kumar <quic_riteshk@quicinc.com>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_abhinavk@quicinc.com, quic_rajeevny@quicinc.com, quic_vproddut@quicinc.com Subject: [PATCH 2/2] arm64: dts: qcom: qcm6490-idp: add display and panel Date: Tue, 16 Jan 2024 15:19:35 +0530 Message-Id: <20240116094935.9988-3-quic_riteshk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240116094935.9988-1-quic_riteshk@quicinc.com> References: <20240116094935.9988-1-quic_riteshk@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SEevayCsF1JDhR8GJCr30yUJJZMM-uWv X-Proofpoint-ORIG-GUID: SEevayCsF1JDhR8GJCr30yUJJZMM-uWv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 spamscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401160077 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788240117365487894 X-GMAIL-MSGID: 1788240117365487894 |
Series |
add display and panel on qcm6490 idp
|
|
Commit Message
Ritesh Kumar
Jan. 16, 2024, 9:49 a.m. UTC
Enable Display Subsystem with Novatek NT36672E Panel
on qcm6490 idp platform.
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++
1 file changed, 100 insertions(+)
Comments
On Tue, 16 Jan 2024 at 11:49, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: > > Enable Display Subsystem with Novatek NT36672E Panel > on qcm6490 idp platform. Is this panel always present on the IDP board or is it an optional addon, like the panels for all the RBn boards? > > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 2a6e4907c5ee..efa5252130a1 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -9,6 +9,7 @@ > #define PM7250B_SID 8 > #define PM7250B_SID1 9 > > +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > #include "sc7280.dtsi" > #include "pm7250b.dtsi" > @@ -38,6 +39,25 @@ > stdout-path = "serial0:115200n8"; > }; > > + lcd_disp_bias: lcd-disp-bias-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "lcd_disp_bias"; > + regulator-min-microvolt = <5500000>; > + regulator-max-microvolt = <5500000>; > + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + pinctrl-names = "default"; > + pinctrl-0 = <&lcd_disp_bias_en>; > + }; > + > + pm8350c_pwm_backlight: backlight { > + compatible = "pwm-backlight"; > + pwms = <&pm8350c_pwm 3 65535>; > + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_lcd_bl_en>; > + }; > + > reserved-memory { > xbl_mem: xbl@80700000 { > reg = <0x0 0x80700000 0x0 0x100000>; > @@ -420,6 +440,86 @@ > }; > }; > > +&gpu { > + status = "disabled"; > +}; > + > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dsi { > + vdda-supply = <&vreg_l6b_1p2>; > + status = "okay"; > + > + panel@0 { > + compatible = "novatek,nt36672e"; > + reg = <0>; > + > + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; > + > + vddi-supply = <&vreg_l8c_1p62>; > + avdd-supply = <&lcd_disp_bias>; > + avee-supply = <&lcd_disp_bias>; > + > + backlight = <&pm8350c_pwm_backlight>; > + > + port { > + panel0_in: endpoint { > + remote-endpoint = <&mdss_dsi0_out>; > + }; > + }; > + }; > +}; > + > +&mdss_dsi0_out { > + remote-endpoint = <&panel0_in>; > + data-lanes = <0 1 2 3>; > +}; > + > +&mdss_dsi_phy { > + vdds-supply = <&vreg_l10c_0p88>; > + status = "okay"; > +}; > + > +&pm7250b_gpios { > + lcd_disp_bias_en: lcd-disp-bias-en-state { > + pins = "gpio2"; > + function = "func1"; > + bias-disable; > + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; > + input-disable; > + output-enable; > + power-source = <0>; > + }; > +}; > + > +&pm8350c_gpios { > + pmic_lcd_bl_en: pmic-lcd-bl-en-state { > + pins = "gpio7"; > + function = "normal"; > + bias-disable; > + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; > + output-low; > + power-source = <0>; > + }; > + > + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { > + pins = "gpio8"; > + function = "func1"; > + bias-disable; > + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; > + output-low; > + power-source = <0>; > + }; > +}; > + > +&pm8350c_pwm { > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_lcd_bl_pwm>; > + status = "okay"; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > -- > 2.17.1 >
On 1/16/24 10:49, Ritesh Kumar wrote: > Enable Display Subsystem with Novatek NT36672E Panel > on qcm6490 idp platform. > > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 2a6e4907c5ee..efa5252130a1 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -9,6 +9,7 @@ > #define PM7250B_SID 8 > #define PM7250B_SID1 9 > > +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > #include "sc7280.dtsi" > #include "pm7250b.dtsi" > @@ -38,6 +39,25 @@ > stdout-path = "serial0:115200n8"; > }; > > + lcd_disp_bias: lcd-disp-bias-regulator { > + compatible = "regulator-fixed"; > + regulator-name = "lcd_disp_bias"; > + regulator-min-microvolt = <5500000>; > + regulator-max-microvolt = <5500000>; > + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + pinctrl-names = "default"; > + pinctrl-0 = <&lcd_disp_bias_en>; property-n property-names all throughout the patch > +&gpu { > + status = "disabled"; > +}; Hm.. generally we disable the GPU in the SoC DT, but that doesn't seem to have happened here.. Thinking about it more, is disabling it here necessary? Does it not fail gracefully? Konrad
On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 1/16/24 10:49, Ritesh Kumar wrote: > > Enable Display Subsystem with Novatek NT36672E Panel > > on qcm6490 idp platform. > > > > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ > > 1 file changed, 100 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > > index 2a6e4907c5ee..efa5252130a1 100644 > > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > > @@ -9,6 +9,7 @@ > > #define PM7250B_SID 8 > > #define PM7250B_SID1 9 > > > > +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > > #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > > #include "sc7280.dtsi" > > #include "pm7250b.dtsi" > > @@ -38,6 +39,25 @@ > > stdout-path = "serial0:115200n8"; > > }; > > > > + lcd_disp_bias: lcd-disp-bias-regulator { > > + compatible = "regulator-fixed"; > > + regulator-name = "lcd_disp_bias"; > > + regulator-min-microvolt = <5500000>; > > + regulator-max-microvolt = <5500000>; > > + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&lcd_disp_bias_en>; > > property-n > property-names > > all throughout the patch > > > +&gpu { > > + status = "disabled"; > > +}; > > Hm.. generally we disable the GPU in the SoC DT, but that doesn't > seem to have happened here.. > > Thinking about it more, is disabling it here necessary? Does it > not fail gracefully? Missed this. I'd say, I don't see a reason to disable it at all. The GPU should be working on sc7280 / qcm4290.
On 1/16/2024 3:28 PM, Dmitry Baryshkov wrote: > On Tue, 16 Jan 2024 at 11:49, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: >> Enable Display Subsystem with Novatek NT36672E Panel >> on qcm6490 idp platform. > Is this panel always present on the IDP board or is it an optional > addon, like the panels for all the RBn boards? This panel is always present on the IDP board. >> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ >> 1 file changed, 100 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 2a6e4907c5ee..efa5252130a1 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -9,6 +9,7 @@ >> #define PM7250B_SID 8 >> #define PM7250B_SID1 9 >> >> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> >> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> >> #include "sc7280.dtsi" >> #include "pm7250b.dtsi" >> @@ -38,6 +39,25 @@ >> stdout-path = "serial0:115200n8"; >> }; >> >> + lcd_disp_bias: lcd-disp-bias-regulator { >> + compatible = "regulator-fixed"; >> + regulator-name = "lcd_disp_bias"; >> + regulator-min-microvolt = <5500000>; >> + regulator-max-microvolt = <5500000>; >> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&lcd_disp_bias_en>; >> + }; >> + >> + pm8350c_pwm_backlight: backlight { >> + compatible = "pwm-backlight"; >> + pwms = <&pm8350c_pwm 3 65535>; >> + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pmic_lcd_bl_en>; >> + }; >> + >> reserved-memory { >> xbl_mem: xbl@80700000 { >> reg = <0x0 0x80700000 0x0 0x100000>; >> @@ -420,6 +440,86 @@ >> }; >> }; >> >> +&gpu { >> + status = "disabled"; >> +}; >> + >> +&mdss { >> + status = "okay"; >> +}; >> + >> +&mdss_dsi { >> + vdda-supply = <&vreg_l6b_1p2>; >> + status = "okay"; >> + >> + panel@0 { >> + compatible = "novatek,nt36672e"; >> + reg = <0>; >> + >> + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; >> + >> + vddi-supply = <&vreg_l8c_1p62>; >> + avdd-supply = <&lcd_disp_bias>; >> + avee-supply = <&lcd_disp_bias>; >> + >> + backlight = <&pm8350c_pwm_backlight>; >> + >> + port { >> + panel0_in: endpoint { >> + remote-endpoint = <&mdss_dsi0_out>; >> + }; >> + }; >> + }; >> +}; >> + >> +&mdss_dsi0_out { >> + remote-endpoint = <&panel0_in>; >> + data-lanes = <0 1 2 3>; >> +}; >> + >> +&mdss_dsi_phy { >> + vdds-supply = <&vreg_l10c_0p88>; >> + status = "okay"; >> +}; >> + >> +&pm7250b_gpios { >> + lcd_disp_bias_en: lcd-disp-bias-en-state { >> + pins = "gpio2"; >> + function = "func1"; >> + bias-disable; >> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; >> + input-disable; >> + output-enable; >> + power-source = <0>; >> + }; >> +}; >> + >> +&pm8350c_gpios { >> + pmic_lcd_bl_en: pmic-lcd-bl-en-state { >> + pins = "gpio7"; >> + function = "normal"; >> + bias-disable; >> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; >> + output-low; >> + power-source = <0>; >> + }; >> + >> + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { >> + pins = "gpio8"; >> + function = "func1"; >> + bias-disable; >> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; >> + output-low; >> + power-source = <0>; >> + }; >> +}; >> + >> +&pm8350c_pwm { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pmic_lcd_bl_pwm>; >> + status = "okay"; >> +}; >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> -- >> 2.17.1 >> Thanks, Ritesh
On Tue, 23 Jan 2024 at 14:43, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: > > > On 1/16/2024 3:28 PM, Dmitry Baryshkov wrote: > > > On Tue, 16 Jan 2024 at 11:49, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: > >> Enable Display Subsystem with Novatek NT36672E Panel > >> on qcm6490 idp platform. > > Is this panel always present on the IDP board or is it an optional > > addon, like the panels for all the RBn boards? > > This panel is always present on the IDP board. Ack, please drop the gpu chunk, fix other review comments and send v2. > > >> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > >> --- > >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ > >> 1 file changed, 100 insertions(+) > >>
On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: > On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> >> On 1/16/24 10:49, Ritesh Kumar wrote: >>> Enable Display Subsystem with Novatek NT36672E Panel >>> on qcm6490 idp platform. >>> >>> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ >>> 1 file changed, 100 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>> index 2a6e4907c5ee..efa5252130a1 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>> @@ -9,6 +9,7 @@ >>> #define PM7250B_SID 8 >>> #define PM7250B_SID1 9 >>> >>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> >>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> >>> #include "sc7280.dtsi" >>> #include "pm7250b.dtsi" >>> @@ -38,6 +39,25 @@ >>> stdout-path = "serial0:115200n8"; >>> }; >>> >>> + lcd_disp_bias: lcd-disp-bias-regulator { >>> + compatible = "regulator-fixed"; >>> + regulator-name = "lcd_disp_bias"; >>> + regulator-min-microvolt = <5500000>; >>> + regulator-max-microvolt = <5500000>; >>> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; >>> + enable-active-high; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&lcd_disp_bias_en>; >> property-n >> property-names >> >> all throughout the patch Thanks, I will update in the new version. >>> +&gpu { >>> + status = "disabled"; >>> +}; >> Hm.. generally we disable the GPU in the SoC DT, but that doesn't >> seem to have happened here.. >> >> Thinking about it more, is disabling it here necessary? Does it >> not fail gracefully? > Missed this. > > I'd say, I don't see a reason to disable it at all. The GPU should be > working on sc7280 / qcm4290. With GPU device node enabled, adreno_bind failure is seen as the "speed_bin" was not populated on QCM6490 target which leads to display bind failure. Spoke with GPU team and on QCM6490 board, only CPU rendering is supported for now and there is no plan to enable GPU rendering in near future. In this regard, what do you suggest 1) Disable GPU in QCM6490 DT (as per the current patch) 2) Disable GPU in the SoC DT, but enable it in other platform DTs. (This will prompt change in all the dt's and we don't have all the devices to test) Please let me know your views on it. Thanks, Ritesh
On Tue, 23 Jan 2024 at 15:43, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: > > > On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: > > > On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > >> > >> > >> On 1/16/24 10:49, Ritesh Kumar wrote: > >>> Enable Display Subsystem with Novatek NT36672E Panel > >>> on qcm6490 idp platform. > >>> > >>> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > >>> --- > >>> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ > >>> 1 file changed, 100 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>> index 2a6e4907c5ee..efa5252130a1 100644 > >>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>> @@ -9,6 +9,7 @@ > >>> #define PM7250B_SID 8 > >>> #define PM7250B_SID1 9 > >>> > >>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > >>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > >>> #include "sc7280.dtsi" > >>> #include "pm7250b.dtsi" > >>> @@ -38,6 +39,25 @@ > >>> stdout-path = "serial0:115200n8"; > >>> }; > >>> > >>> + lcd_disp_bias: lcd-disp-bias-regulator { > >>> + compatible = "regulator-fixed"; > >>> + regulator-name = "lcd_disp_bias"; > >>> + regulator-min-microvolt = <5500000>; > >>> + regulator-max-microvolt = <5500000>; > >>> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; > >>> + enable-active-high; > >>> + pinctrl-names = "default"; > >>> + pinctrl-0 = <&lcd_disp_bias_en>; > >> property-n > >> property-names > >> > >> all throughout the patch > > Thanks, I will update in the new version. > > >>> +&gpu { > >>> + status = "disabled"; > >>> +}; > >> Hm.. generally we disable the GPU in the SoC DT, but that doesn't > >> seem to have happened here.. > >> > >> Thinking about it more, is disabling it here necessary? Does it > >> not fail gracefully? > > Missed this. > > > > I'd say, I don't see a reason to disable it at all. The GPU should be > > working on sc7280 / qcm4290. > > With GPU device node enabled, adreno_bind failure is seen as the > "speed_bin" was not populated on QCM6490 target which leads to display > bind failure. Excuse me please. The GPU node for sc7280 already has speed_bin, which points to qfprom + 0x1e9, bits 5 to 9. Do you mean that qcm6490 uses different speed bin location? Or different values for the speed bins? > Spoke with GPU team and on QCM6490 board, only CPU rendering is > supported for now and there is no plan to enable GPU rendering in near > future. This sounds like having the feature disabled for no particular reason. Both the kernel and Mesa have supported the Adreno 635 for quite a while. > In this regard, what do you suggest > > 1) Disable GPU in QCM6490 DT (as per the current patch) > 2) Disable GPU in the SoC DT, but enable it in other platform DTs. (This > will prompt change in all the dt's and we don't have all the devices to > test) The second option definitely follows what is present on other platforms. > Please let me know your views on it. Please enable the GPU instead.
On 1/23/24 16:12, Dmitry Baryshkov wrote: > On Tue, 23 Jan 2024 at 15:43, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: >> >> >> On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: >> >>> On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >>>> >>>> >>>> On 1/16/24 10:49, Ritesh Kumar wrote: >>>>> Enable Display Subsystem with Novatek NT36672E Panel >>>>> on qcm6490 idp platform. >>>>> >>>>> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 +++++++++++++++++++++++ >>>>> 1 file changed, 100 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>> index 2a6e4907c5ee..efa5252130a1 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>> @@ -9,6 +9,7 @@ >>>>> #define PM7250B_SID 8 >>>>> #define PM7250B_SID1 9 >>>>> >>>>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> >>>>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> >>>>> #include "sc7280.dtsi" >>>>> #include "pm7250b.dtsi" >>>>> @@ -38,6 +39,25 @@ >>>>> stdout-path = "serial0:115200n8"; >>>>> }; >>>>> >>>>> + lcd_disp_bias: lcd-disp-bias-regulator { >>>>> + compatible = "regulator-fixed"; >>>>> + regulator-name = "lcd_disp_bias"; >>>>> + regulator-min-microvolt = <5500000>; >>>>> + regulator-max-microvolt = <5500000>; >>>>> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; >>>>> + enable-active-high; >>>>> + pinctrl-names = "default"; >>>>> + pinctrl-0 = <&lcd_disp_bias_en>; >>>> property-n >>>> property-names >>>> >>>> all throughout the patch >> >> Thanks, I will update in the new version. >> >>>>> +&gpu { >>>>> + status = "disabled"; >>>>> +}; >>>> Hm.. generally we disable the GPU in the SoC DT, but that doesn't >>>> seem to have happened here.. >>>> >>>> Thinking about it more, is disabling it here necessary? Does it >>>> not fail gracefully? >>> Missed this. >>> >>> I'd say, I don't see a reason to disable it at all. The GPU should be >>> working on sc7280 / qcm4290. >> >> With GPU device node enabled, adreno_bind failure is seen as the >> "speed_bin" was not populated on QCM6490 target which leads to display >> bind failure. > > Excuse me please. The GPU node for sc7280 already has speed_bin, which > points to qfprom + 0x1e9, bits 5 to 9. > > Do you mean that qcm6490 uses different speed bin location? Or > different values for the speed bins? > >> Spoke with GPU team and on QCM6490 board, only CPU rendering is >> supported for now and there is no plan to enable GPU rendering in near >> future. > > This sounds like having the feature disabled for no particular reason. > Both the kernel and Mesa have supported the Adreno 635 for quite a > while. 643 [1], [2] > >> In this regard, what do you suggest >> >> 1) Disable GPU in QCM6490 DT (as per the current patch) >> 2) Disable GPU in the SoC DT, but enable it in other platform DTs. (This >> will prompt change in all the dt's and we don't have all the devices to >> test) > > The second option definitely follows what is present on other platforms. > >> Please let me know your views on it. > > Please enable the GPU instead. +1 Konrad [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408/diffs?commit_id=b1e851d66c3a3e53f1a464023f675f3f6cbd3503 [2] https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/
On 1/23/2024 11:34 PM, Konrad Dybcio wrote: > > > On 1/23/24 16:12, Dmitry Baryshkov wrote: >> On Tue, 23 Jan 2024 at 15:43, Ritesh Kumar <quic_riteshk@quicinc.com> >> wrote: >>> >>> >>> On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: >>> >>>> On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio >>>> <konrad.dybcio@linaro.org> wrote: >>>>> >>>>> >>>>> On 1/16/24 10:49, Ritesh Kumar wrote: >>>>>> Enable Display Subsystem with Novatek NT36672E Panel >>>>>> on qcm6490 idp platform. >>>>>> >>>>>> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 >>>>>> +++++++++++++++++++++++ >>>>>> 1 file changed, 100 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> index 2a6e4907c5ee..efa5252130a1 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> @@ -9,6 +9,7 @@ >>>>>> #define PM7250B_SID 8 >>>>>> #define PM7250B_SID1 9 >>>>>> >>>>>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> >>>>>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> >>>>>> #include "sc7280.dtsi" >>>>>> #include "pm7250b.dtsi" >>>>>> @@ -38,6 +39,25 @@ >>>>>> stdout-path = "serial0:115200n8"; >>>>>> }; >>>>>> >>>>>> + lcd_disp_bias: lcd-disp-bias-regulator { >>>>>> + compatible = "regulator-fixed"; >>>>>> + regulator-name = "lcd_disp_bias"; >>>>>> + regulator-min-microvolt = <5500000>; >>>>>> + regulator-max-microvolt = <5500000>; >>>>>> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; >>>>>> + enable-active-high; >>>>>> + pinctrl-names = "default"; >>>>>> + pinctrl-0 = <&lcd_disp_bias_en>; >>>>> property-n >>>>> property-names >>>>> >>>>> all throughout the patch >>> >>> Thanks, I will update in the new version. >>> >>>>>> +&gpu { >>>>>> + status = "disabled"; >>>>>> +}; >>>>> Hm.. generally we disable the GPU in the SoC DT, but that doesn't >>>>> seem to have happened here.. >>>>> >>>>> Thinking about it more, is disabling it here necessary? Does it >>>>> not fail gracefully? >>>> Missed this. >>>> >>>> I'd say, I don't see a reason to disable it at all. The GPU should be >>>> working on sc7280 / qcm4290. >>> >>> With GPU device node enabled, adreno_bind failure is seen as the >>> "speed_bin" was not populated on QCM6490 target which leads to display >>> bind failure. >> >> Excuse me please. The GPU node for sc7280 already has speed_bin, which >> points to qfprom + 0x1e9, bits 5 to 9. >> >> Do you mean that qcm6490 uses different speed bin location? Or >> different values for the speed bins? >> >>> Spoke with GPU team and on QCM6490 board, only CPU rendering is >>> supported for now and there is no plan to enable GPU rendering in near >>> future. >> >> This sounds like having the feature disabled for no particular reason. >> Both the kernel and Mesa have supported the Adreno 635 for quite a >> while. > > 643 [1], [2] > >> >>> In this regard, what do you suggest >>> >>> 1) Disable GPU in QCM6490 DT (as per the current patch) >>> 2) Disable GPU in the SoC DT, but enable it in other platform DTs. >>> (This >>> will prompt change in all the dt's and we don't have all the devices to >>> test) >> >> The second option definitely follows what is present on other platforms. >> >>> Please let me know your views on it. >> >> Please enable the GPU instead. > > +1 > > Konrad > > [1] > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408/diffs?commit_id=b1e851d66c3a3e53f1a464023f675f3f6cbd3503 > [2] > https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ Thanks for the help. After applying missing patches from series https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ in my local build, GPU is working fine. GPU disablement change is not needed. I will send new version of patch removing GPU part and addressing other review comments. Thanks, Ritesh
On Mon, 12 Feb 2024 at 14:28, Ritesh Kumar <quic_riteshk@quicinc.com> wrote: > > > On 1/23/2024 11:34 PM, Konrad Dybcio wrote: > > > > > > On 1/23/24 16:12, Dmitry Baryshkov wrote: > >> On Tue, 23 Jan 2024 at 15:43, Ritesh Kumar <quic_riteshk@quicinc.com> > >> wrote: > >>> > >>> > >>> On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: > >>> > >>>> On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio > >>>> <konrad.dybcio@linaro.org> wrote: > >>>>> > >>>>> > >>>>> On 1/16/24 10:49, Ritesh Kumar wrote: > >>>>>> Enable Display Subsystem with Novatek NT36672E Panel > >>>>>> on qcm6490 idp platform. > >>>>>> > >>>>>> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com> > >>>>>> --- > >>>>>> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 > >>>>>> +++++++++++++++++++++++ > >>>>>> 1 file changed, 100 insertions(+) > >>>>>> > >>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>>>>> b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>>>>> index 2a6e4907c5ee..efa5252130a1 100644 > >>>>>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>>>>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >>>>>> @@ -9,6 +9,7 @@ > >>>>>> #define PM7250B_SID 8 > >>>>>> #define PM7250B_SID1 9 > >>>>>> > >>>>>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> > >>>>>> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> > >>>>>> #include "sc7280.dtsi" > >>>>>> #include "pm7250b.dtsi" > >>>>>> @@ -38,6 +39,25 @@ > >>>>>> stdout-path = "serial0:115200n8"; > >>>>>> }; > >>>>>> > >>>>>> + lcd_disp_bias: lcd-disp-bias-regulator { > >>>>>> + compatible = "regulator-fixed"; > >>>>>> + regulator-name = "lcd_disp_bias"; > >>>>>> + regulator-min-microvolt = <5500000>; > >>>>>> + regulator-max-microvolt = <5500000>; > >>>>>> + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; > >>>>>> + enable-active-high; > >>>>>> + pinctrl-names = "default"; > >>>>>> + pinctrl-0 = <&lcd_disp_bias_en>; > >>>>> property-n > >>>>> property-names > >>>>> > >>>>> all throughout the patch > >>> > >>> Thanks, I will update in the new version. > >>> > >>>>>> +&gpu { > >>>>>> + status = "disabled"; > >>>>>> +}; > >>>>> Hm.. generally we disable the GPU in the SoC DT, but that doesn't > >>>>> seem to have happened here.. > >>>>> > >>>>> Thinking about it more, is disabling it here necessary? Does it > >>>>> not fail gracefully? > >>>> Missed this. > >>>> > >>>> I'd say, I don't see a reason to disable it at all. The GPU should be > >>>> working on sc7280 / qcm4290. > >>> > >>> With GPU device node enabled, adreno_bind failure is seen as the > >>> "speed_bin" was not populated on QCM6490 target which leads to display > >>> bind failure. > >> > >> Excuse me please. The GPU node for sc7280 already has speed_bin, which > >> points to qfprom + 0x1e9, bits 5 to 9. > >> > >> Do you mean that qcm6490 uses different speed bin location? Or > >> different values for the speed bins? > >> > >>> Spoke with GPU team and on QCM6490 board, only CPU rendering is > >>> supported for now and there is no plan to enable GPU rendering in near > >>> future. > >> > >> This sounds like having the feature disabled for no particular reason. > >> Both the kernel and Mesa have supported the Adreno 635 for quite a > >> while. > > > > 643 [1], [2] > > > >> > >>> In this regard, what do you suggest > >>> > >>> 1) Disable GPU in QCM6490 DT (as per the current patch) > >>> 2) Disable GPU in the SoC DT, but enable it in other platform DTs. > >>> (This > >>> will prompt change in all the dt's and we don't have all the devices to > >>> test) > >> > >> The second option definitely follows what is present on other platforms. > >> > >>> Please let me know your views on it. > >> > >> Please enable the GPU instead. > > > > +1 > > > > Konrad > > > > [1] > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408/diffs?commit_id=b1e851d66c3a3e53f1a464023f675f3f6cbd3503 > > [2] > > https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ > > Thanks for the help. After applying missing patches from series > https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ > in my local build, GPU is working fine. GPU disablement change is not > needed. I will send new version of patch removing GPU part and > addressing other review comments. Thank you!
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 2a6e4907c5ee..efa5252130a1 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc7280.dtsi" #include "pm7250b.dtsi" @@ -38,6 +39,25 @@ stdout-path = "serial0:115200n8"; }; + lcd_disp_bias: lcd-disp-bias-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_disp_bias"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_disp_bias_en>; + }; + + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8350c_pwm 3 65535>; + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_lcd_bl_en>; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -420,6 +440,86 @@ }; }; +&gpu { + status = "disabled"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p62>; + avdd-supply = <&lcd_disp_bias>; + avee-supply = <&lcd_disp_bias>; + + backlight = <&pm8350c_pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + +&pm7250b_gpios { + lcd_disp_bias_en: lcd-disp-bias-en-state { + pins = "gpio2"; + function = "func1"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_gpios { + pmic_lcd_bl_en: pmic-lcd-bl-en-state { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + output-low; + power-source = <0>; + }; + + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + output-low; + power-source = <0>; + }; +}; + +&pm8350c_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_lcd_bl_pwm>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; };