diff mbox series

[33/35] arm: improve tests and fix vrmlaldavhaq*

Message ID 20221117163809.1009526-34-andrea.corallo@arm.com
State Accepted
Headers
Series arm: rework MVE testsuite and rework backend where necessary (1st chunk) |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Andrea Corallo Nov. 17, 2022, 4:38 p.m. UTC 
  gcc/ChangeLog:

	* config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
	mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve test.
	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.
---
 gcc/config/arm/mve.md                         |  4 +-
 .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c   | 24 ++++++++++-
 .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c   | 40 ++++++++++++++++++-
 3 files changed, 62 insertions(+), 6 deletions(-)

Comments

Kyrylo Tkachov Nov. 22, 2022, 5:03 p.m. UTC | #1 
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Thursday, November 17, 2022 4:38 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 33/35] arm: improve tests and fix vrmlaldavhaq*
> 
> gcc/ChangeLog:
> 
> 	* config/arm/mve.md (mve_vrmlaldavhq_<supf>v4si,
> 	mve_vrmlaldavhaq_<supf>v4si): Fix spacing vs tabs.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c: Improve
> test.
> 	* gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c: Likewise.

Ok.
Thanks,
Kyrill

> ---
>  gcc/config/arm/mve.md                         |  4 +-
>  .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c   | 24 ++++++++++-
>  .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c   | 40 ++++++++++++++++++-
>  3 files changed, 62 insertions(+), 6 deletions(-)
> 
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index d2ffae6a425..b5e6da4b133 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -2543,7 +2543,7 @@ (define_insn "mve_vrmlaldavhq_<supf>v4si"
>  	 VRMLALDAVHQ))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
> +  "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2"
>    [(set_attr "type" "mve_move")
>  ])
> 
> @@ -2649,7 +2649,7 @@ (define_insn "mve_vrmlaldavhaq_<supf>v4si"
>  	 VRMLALDAVHAQ))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
> +  "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3"
>    [(set_attr "type" "mve_move")
>  ])
> 
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
> index 263d3509771..dec4a969dfe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
> @@ -1,21 +1,41 @@
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +**	vpst(?:	@.*|)
> +**	...
> +**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+,
> q[0-9]+(?:	@.*|)
> +**	...
> +*/
>  int64_t
>  foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
>  {
>    return vrmlaldavhaq_p_s32 (a, b, c, p);
>  }
> 
> -/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +**	vpst(?:	@.*|)
> +**	...
> +**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+,
> q[0-9]+(?:	@.*|)
> +**	...
> +*/
>  int64_t
>  foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
>  {
>    return vrmlaldavhaq_p (a, b, c, p);
>  }
> 
> -/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
> index 83ab68c001b..f3c8bfd121c 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
> @@ -1,21 +1,57 @@
>  /* { dg-require-effective-target arm_v8_1m_mve_ok } */
>  /* { dg-add-options arm_v8_1m_mve } */
>  /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> 
>  #include "arm_mve.h"
> 
> +/*
> +**foo:
> +**	...
> +**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +**	vpst(?:	@.*|)
> +**	...
> +**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+,
> q[0-9]+(?:	@.*|)
> +**	...
> +*/
>  uint64_t
>  foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
>  {
>    return vrmlaldavhaq_p_u32 (a, b, c, p);
>  }
> 
> -/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
> 
> +/*
> +**foo1:
> +**	...
> +**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +**	vpst(?:	@.*|)
> +**	...
> +**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+,
> q[0-9]+(?:	@.*|)
> +**	...
> +*/
>  uint64_t
>  foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
>  {
>    return vrmlaldavhaq_p (a, b, c, p);
>  }
> 
> -/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
> +/*
> +**foo2:
> +**	...
> +**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
> +**	...
> +**	vpst(?:	@.*|)
> +**	...
> +**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+,
> q[0-9]+(?:	@.*|)
> +**	...
> +*/
> +uint64_t
> +foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
> +{
> +  return vrmlaldavhaq_p (1, b, c, p);
> +}
> +
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> \ No newline at end of file
> --
> 2.25.1
diff mbox series

Patch

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d2ffae6a425..b5e6da4b133 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2543,7 +2543,7 @@  (define_insn "mve_vrmlaldavhq_<supf>v4si"
 	 VRMLALDAVHQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavh.<supf>32 %Q0, %R0, %q1, %q2"
+  "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -2649,7 +2649,7 @@  (define_insn "mve_vrmlaldavhaq_<supf>v4si"
 	 VRMLALDAVHAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vrmlaldavha.<supf>32 %Q0, %R0, %q2, %q3"
+  "vrmlaldavha.<supf>32\t%Q0, %R0, %q2, %q3"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
index 263d3509771..dec4a969dfe 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c
@@ -1,21 +1,41 @@ 
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_s32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.s32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 int64_t
 foo1 (int64_t a, int32x4_t b, int32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.s32"  }  } */
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
index 83ab68c001b..f3c8bfd121c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c
@@ -1,21 +1,57 @@ 
 /* { dg-require-effective-target arm_v8_1m_mve_ok } */
 /* { dg-add-options arm_v8_1m_mve } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+/*
+**foo:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p_u32 (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
 
+/*
+**foo1:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
 uint64_t
 foo1 (uint64_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p)
 {
   return vrmlaldavhaq_p (a, b, c, p);
 }
 
-/* { dg-final { scan-assembler "vrmlaldavhat.u32"  }  } */
+/*
+**foo2:
+**	...
+**	vmsr	p0, (?:ip|fp|r[0-9]+)(?:	@.*|)
+**	...
+**	vpst(?:	@.*|)
+**	...
+**	vrmlaldavhat.u32	(?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?:	@.*|)
+**	...
+*/
+uint64_t
+foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p)
+{
+  return vrmlaldavhaq_p (1, b, c, p);
+}
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file