Message ID | 20240110112059.2498-6-quic_luoj@quicinc.com |
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State | New |
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Wed, 10 Jan 2024 11:21:37 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:33 -0800 From: Luo Jie <quic_luoj@quicinc.com> To: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>, <quic_kkumarcs@quicinc.com>, <quic_suruchia@quicinc.com>, <quic_soni@quicinc.com>, <quic_pavir@quicinc.com>, <quic_souravp@quicinc.com>, <quic_linchen@quicinc.com>, <quic_leiwei@quicinc.com> Subject: [PATCH 5/6] arm64: dts: qcom: ipq5332: Add RDP441 board device tree Date: Wed, 10 Jan 2024 19:20:58 +0800 Message-ID: <20240110112059.2498-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sAbTDsgBYlvv8YlsnNYBgKDcn9gvsDMC X-Proofpoint-GUID: sAbTDsgBYlvv8YlsnNYBgKDcn9gvsDMC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=902 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787702400178177400 X-GMAIL-MSGID: 1787702400178177400 |
Series |
Add PPE device tree node for Qualcomm IPQ SoC
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Commit Message
Jie Luo
Jan. 10, 2024, 11:20 a.m. UTC
From: Lei Wei <quic_leiwei@quicinc.com> RDP441 board has onboard QCA8386 switch and 10G SFP port. Signed-off-by: Lei Wei <quic_leiwei@quicinc.com> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ 1 file changed, 51 insertions(+)
Comments
On 10/01/2024 12:20, Luo Jie wrote: > From: Lei Wei <quic_leiwei@quicinc.com> > > RDP441 board has onboard QCA8386 switch and 10G SFP port. > > Signed-off-by: Lei Wei <quic_leiwei@quicinc.com> > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > index 846413817e9a..d51968e9d601 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts > @@ -12,6 +12,15 @@ > / { > model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; > compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; > + > + soc@0 { Nope, DTS does not define soc nodes. > + sfp1: sfp-1 { Why is this soc? Where is the MMIO address? > + compatible = "sff,sfp"; > + i2c-bus = <&blsp1_i2c1>; > + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; > + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; > + }; > + }; > }; > > &blsp1_i2c1 { > @@ -63,3 +72,45 @@ data-pins { > }; > }; > }; > + > +&qcom_ppe { > + qcom,port_phyinfo { Eh... We talk now about basics: please don't post downstream code, but first clean it up from all the junk. All the basic issues which you have in downstream and which we do not accept upstream. I do not believe that this code passed internal review. NAK. Best regards, Krzysztof
On 1/10/2024 7:57 PM, Krzysztof Kozlowski wrote: > On 10/01/2024 12:20, Luo Jie wrote: >> From: Lei Wei <quic_leiwei@quicinc.com> >> >> RDP441 board has onboard QCA8386 switch and 10G SFP port. >> >> Signed-off-by: Lei Wei <quic_leiwei@quicinc.com> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> index 846413817e9a..d51968e9d601 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts >> @@ -12,6 +12,15 @@ >> / { >> model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; >> compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; >> + >> + soc@0 { > > Nope, DTS does not define soc nodes. > OK, I will remove the soc node in the DTS file. SFP node should not be inside the soc node. >> + sfp1: sfp-1 { > > Why is this soc? Where is the MMIO address? Sure, SoC node should not be required. I will remove the soc node. > >> + compatible = "sff,sfp"; >> + i2c-bus = <&blsp1_i2c1>; >> + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; >> + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; >> + }; >> + }; >> }; >> >> &blsp1_i2c1 { >> @@ -63,3 +72,45 @@ data-pins { >> }; >> }; >> }; >> + >> +&qcom_ppe { >> + qcom,port_phyinfo { > > Eh... We talk now about basics: please don't post downstream code, but > first clean it up from all the junk. All the basic issues which you have > in downstream and which we do not accept upstream. > > I do not believe that this code passed internal review. > > NAK. Sure, got it. I will follow the upstream principles to use generic node name. > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..d51968e9d601 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -12,6 +12,15 @@ / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + soc@0 { + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&blsp1_i2c1>; + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; + }; + }; }; &blsp1_i2c1 { @@ -63,3 +72,45 @@ data-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + }; +}; + +&mdio { + status = "okay"; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + phy0: ethernet-phy@0 { + reg = <1>; + }; + + phy1: ethernet-phy@1 { + reg = <2>; + }; + + phy2: ethernet-phy@2 { + reg = <3>; + }; + + phy3: ethernet-phy@3 { + reg = <4>; + }; +};