[DO,NOT,MERGE,2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs
Message ID | 20240115125716.560363-3-devarsht@ti.com |
---|---|
State | New |
Headers |
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[147.75.48.161]) by mx.google.com with ESMTPS id h22-20020a635316000000b005cda5e4a862si8943572pgb.258.2024.01.15.04.58.19 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 04:58:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rq8SDkeN; spf=pass (google.com: domain of linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-25981-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id CF7CBB2139C for <ouuuleilei@gmail.com>; Mon, 15 Jan 2024 12:58:18 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 253221754E; Mon, 15 Jan 2024 12:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="rq8SDkeN" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAEAB171D8; Mon, 15 Jan 2024 12:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvLMd112244; Mon, 15 Jan 2024 06:57:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705323441; bh=3Osuk5K0i7HWxwinhFXlIBGatS8OzdMtUhxrEy62/3M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rq8SDkeNaTsb/gYCbLlLCaoNrxadGaZlmeBI6rPjWF4+Te+xCGyA/FdmYfoLHvao1 tvlfVug4KLtDvn4Bo7M2I8dKj8ORoKR51vbYa0fCeeoaqtlxTlMJ2T1+Umk+qO+ihV 7aLagIQMPsxfXbqfsbmMcIQc4rd1q6kSwI7FoP4s= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40FCvLYI123671 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jan 2024 06:57:21 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jan 2024 06:57:20 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jan 2024 06:57:20 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvJpS128487; Mon, 15 Jan 2024 06:57:20 -0600 From: Devarsh Thakkar <devarsht@ti.com> To: <jyri.sarha@iki.fi>, <tomi.valkeinen@ideasonboard.com>, <airlied@gmail.com>, <daniel@ffwll.ch>, <maarten.lankhorst@linux.intel.com>, <mripard@kernel.org>, <tzimmermann@suse.de>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> CC: <praneeth@ti.com>, <nm@ti.com>, <vigneshr@ti.com>, <a-bhatia1@ti.com>, <j-luthra@ti.com>, <kristo@kernel.org>, <devarsht@ti.com> Subject: [DO NOT MERGE PATCH 2/2] arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs Date: Mon, 15 Jan 2024 18:27:16 +0530 Message-ID: <20240115125716.560363-3-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115125716.560363-1-devarsht@ti.com> References: <20240115125716.560363-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788161294104388626 X-GMAIL-MSGID: 1788161294104388626 |
Series |
Add common1 register space for TI Keystone displays
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Commit Message
Devarsh Thakkar
Jan. 15, 2024, 12:57 p.m. UTC
This adds common1 register space for AM62x and AM65x SoC's which are using
TI's Keystone display hardware and supporting it as described in
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml.
This region is documented in respective Technical Reference Manuals [1].
[1]:
AM62x TRM:
https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers)
AM65x TRM:
https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers)
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++--
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
Comments
On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > This adds common1 register space for AM62x and AM65x SoC's which are using > TI's Keystone display hardware and supporting it as described in > Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > > This region is documented in respective Technical Reference Manuals [1]. > > [1]: > AM62x TRM: > https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > > AM65x TRM: > https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > > Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > --- "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot be merged? What's the problem with it? Cheers, Conor. > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index 464b7565d085..298bf8d5de8c 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -779,9 +779,10 @@ dss: dss@30200000 { > <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ > <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ > <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ > - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ > + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ > + <0x00 0x30201000 0x00 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 186 6>, > <&dss_vp1_clk>, > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index fcea54465636..5b2d4365b911 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { > <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ > <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ > <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ > - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ > + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ > + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ > reg-names = "common", "vidl1", "vid", > - "ovr1", "ovr2", "vp1", "vp2"; > + "ovr1", "ovr2", "vp1", "vp2", "common1"; > > ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; > > -- > 2.34.1 >
Hi Conor, Thanks for the review. On 15/01/24 21:44, Conor Dooley wrote: > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: >> This adds common1 register space for AM62x and AM65x SoC's which are using >> TI's Keystone display hardware and supporting it as described in >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. >> >> This region is documented in respective Technical Reference Manuals [1]. >> >> [1]: >> AM62x TRM: >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) >> >> AM65x TRM: >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) >> >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> >> --- > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > be merged? What's the problem with it? > No problem as such from my point of view, but this is the process I follow since maintainer trees for device-tree file and bindings are different. I generally mark a [DO NOT MERGE] tag for device-tree file patches until binding patch gets merged so that the device-tree patches don't get applied by mistake if binding patch has some pending comments. Once binding patch gets merged, I re-send the device-tree file patches again to respective list. Regards Devarsh > Cheers, > Conor. > >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- >> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- >> 2 files changed, 6 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> index 464b7565d085..298bf8d5de8c 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> @@ -779,9 +779,10 @@ dss: dss@30200000 { >> <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ >> <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ >> <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ >> - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ >> + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ >> + <0x00 0x30201000 0x00 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 186 6>, >> <&dss_vp1_clk>, >> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> index fcea54465636..5b2d4365b911 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { >> <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ >> <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ >> <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ >> - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ >> + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ >> + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ >> reg-names = "common", "vidl1", "vid", >> - "ovr1", "ovr2", "vp1", "vp2"; >> + "ovr1", "ovr2", "vp1", "vp2", "common1"; >> >> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; >> >> -- >> 2.34.1 >>
On Tue, Jan 16, 2024 at 02:48:53PM +0530, Devarsh Thakkar wrote: > Hi Conor, > > Thanks for the review. > > On 15/01/24 21:44, Conor Dooley wrote: > > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > >> This adds common1 register space for AM62x and AM65x SoC's which are using > >> TI's Keystone display hardware and supporting it as described in > >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > >> > >> This region is documented in respective Technical Reference Manuals [1]. > >> > >> [1]: > >> AM62x TRM: > >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > >> > >> AM65x TRM: > >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > >> > >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > >> --- > > > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > > be merged? What's the problem with it? > > > > No problem as such from my point of view, but this is the process I follow > since maintainer trees for device-tree file and bindings are different. I > generally mark a [DO NOT MERGE] tag for device-tree file patches until binding > patch gets merged so that the device-tree patches don't get applied by mistake > if binding patch has some pending comments. > > Once binding patch gets merged, I re-send the device-tree file patches again > to respective list. I see. Please note this in your patches, under the --- line, in the future to avoid confusion.
On Tue, Jan 16, 2024 at 02:48:53PM +0530, Devarsh Thakkar wrote: > Hi Conor, > > Thanks for the review. > > On 15/01/24 21:44, Conor Dooley wrote: > > On Mon, Jan 15, 2024 at 06:27:16PM +0530, Devarsh Thakkar wrote: > >> This adds common1 register space for AM62x and AM65x SoC's which are using > >> TI's Keystone display hardware and supporting it as described in > >> Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml. > >> > >> This region is documented in respective Technical Reference Manuals [1]. > >> > >> [1]: > >> AM62x TRM: > >> https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers) > >> > >> AM65x TRM: > >> https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers) > >> > >> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> > >> --- > > > > "[DO NOT MERGE PATCH 2/2]" but no rationale here as to why this cannot > > be merged? What's the problem with it? > > > > No problem as such from my point of view, but this is the process I follow > since maintainer trees for device-tree file and bindings are different. I > generally mark a [DO NOT MERGE] tag for device-tree file patches until binding > patch gets merged so that the device-tree patches don't get applied by mistake > if binding patch has some pending comments. RFC is the tag for "don't merge". Don't make-up your own tags. Rob
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 464b7565d085..298bf8d5de8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -779,9 +779,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>, diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fcea54465636..5b2d4365b911 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -1019,9 +1019,10 @@ dss: dss@4a00000 { <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;