Message ID | 20221118011714.70877-6-hal.feng@starfivetech.com |
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State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i19-20020a05640242d300b00453a0393deasi2370139edc.368.2022.11.17.17.35.10; Thu, 17 Nov 2022 17:35:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240667AbiKRBcM convert rfc822-to-8bit (ORCPT <rfc822;a1648639935@gmail.com> + 99 others); Thu, 17 Nov 2022 20:32:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240980AbiKRBbX (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 17 Nov 2022 20:31:23 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3AAF720A1; Thu, 17 Nov 2022 17:31:22 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 47A9024E211; Fri, 18 Nov 2022 09:17:22 +0800 (CST) Received: from EXMBX072.cuchost.com (172.16.6.82) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:17:22 +0800 Received: from ubuntu.localdomain (183.27.96.116) by EXMBX072.cuchost.com (172.16.6.82) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:17:21 +0800 From: Hal Feng <hal.feng@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org> CC: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Ben Dooks <ben.dooks@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, "Linus Walleij" <linus.walleij@linaro.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 5/8] soc: sifive: ccache: Add StarFive JH7110 support Date: Fri, 18 Nov 2022 09:17:11 +0800 Message-ID: <20221118011714.70877-6-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118011714.70877-1-hal.feng@starfivetech.com> References: <20221118011714.70877-1-hal.feng@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.96.116] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX072.cuchost.com (172.16.6.82) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749795821162858901?= X-GMAIL-MSGID: =?utf-8?q?1749795821162858901?= |
Series |
Basic device tree support for StarFive JH7110 RISC-V SoC
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Commit Message
Hal Feng
Nov. 18, 2022, 1:17 a.m. UTC
From: Emil Renner Berthing <kernel@esmil.dk> This adds support for the StarFive JH7110 SoC which also features this SiFive cache controller. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- arch/riscv/Kconfig.socs | 1 + drivers/soc/Makefile | 2 +- drivers/soc/sifive/Kconfig | 2 +- drivers/soc/sifive/sifive_ccache.c | 1 + 4 files changed, 4 insertions(+), 2 deletions(-)
Comments
Hey Emil/Hal, On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote: > From: Emil Renner Berthing <kernel@esmil.dk> > > This adds support for the StarFive JH7110 SoC which also > features this SiFive cache controller. > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > arch/riscv/Kconfig.socs | 1 + > drivers/soc/Makefile | 2 +- > drivers/soc/sifive/Kconfig | 2 +- > drivers/soc/sifive/sifive_ccache.c | 1 + > 4 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..5a40e05f8cab 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -22,6 +22,7 @@ config SOC_STARFIVE > bool "StarFive SoCs" > select PINCTRL > select RESET_CONTROLLER > + select SIFIVE_CCACHE Please no. I am trying to get rid of these selects + I cannot figure out why this driver is so important that you *need* to select it. Surely the SoC is useable without it? Is this a hang over from your vendor tree that uses the driver to do non-coherent stuff for the jh7100? > select SIFIVE_PLIC > help > This enables support for StarFive SoC platform hardware. > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > index 69ba6508cf2c..534669840858 100644 > --- a/drivers/soc/Makefile > +++ b/drivers/soc/Makefile > @@ -26,7 +26,7 @@ obj-y += qcom/ > obj-y += renesas/ > obj-y += rockchip/ > obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > -obj-$(CONFIG_SOC_SIFIVE) += sifive/ > +obj-y += sifive/ This bit is fine. > obj-y += sunxi/ > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > obj-y += ti/ > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > index ed4c571f8771..e86870be34c9 100644 > --- a/drivers/soc/sifive/Kconfig > +++ b/drivers/soc/sifive/Kconfig > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > > -if SOC_SIFIVE > +if SOC_SIFIVE || SOC_STARFIVE As I suppose is this - but hardly scalable. I suppose it doesn't really matter. > config SIFIVE_CCACHE > bool "Sifive Composable Cache controller" > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > index 1c171150e878..9489d1a90fbc 100644 > --- a/drivers/soc/sifive/sifive_ccache.c > +++ b/drivers/soc/sifive/sifive_ccache.c > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { > { .compatible = "sifive,fu540-c000-ccache" }, > { .compatible = "sifive,fu740-c000-ccache" }, > { .compatible = "sifive,ccache0" }, > + { .compatible = "starfive,jh7110-ccache" }, Per my second reply to the previous patch, I am not sure why you do not just have a fallback compatible in the binding/dt for the fu740 ccache since you appear to have identical configuration? Thanks, Conor.
On Fri, 18 Nov 2022 at 02:17, Hal Feng <hal.feng@starfivetech.com> wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > This adds support for the StarFive JH7110 SoC which also > features this SiFive cache controller. > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- I'm fine with this, but it would be great if you could add the jh7100 support at the same time like the original patch did. > arch/riscv/Kconfig.socs | 1 + > drivers/soc/Makefile | 2 +- > drivers/soc/sifive/Kconfig | 2 +- > drivers/soc/sifive/sifive_ccache.c | 1 + > 4 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..5a40e05f8cab 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -22,6 +22,7 @@ config SOC_STARFIVE > bool "StarFive SoCs" > select PINCTRL > select RESET_CONTROLLER > + select SIFIVE_CCACHE > select SIFIVE_PLIC > help > This enables support for StarFive SoC platform hardware. > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > index 69ba6508cf2c..534669840858 100644 > --- a/drivers/soc/Makefile > +++ b/drivers/soc/Makefile > @@ -26,7 +26,7 @@ obj-y += qcom/ > obj-y += renesas/ > obj-y += rockchip/ > obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > -obj-$(CONFIG_SOC_SIFIVE) += sifive/ > +obj-y += sifive/ > obj-y += sunxi/ > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > obj-y += ti/ > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > index ed4c571f8771..e86870be34c9 100644 > --- a/drivers/soc/sifive/Kconfig > +++ b/drivers/soc/sifive/Kconfig > @@ -1,6 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > > -if SOC_SIFIVE > +if SOC_SIFIVE || SOC_STARFIVE > > config SIFIVE_CCACHE > bool "Sifive Composable Cache controller" > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > index 1c171150e878..9489d1a90fbc 100644 > --- a/drivers/soc/sifive/sifive_ccache.c > +++ b/drivers/soc/sifive/sifive_ccache.c > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { > { .compatible = "sifive,fu540-c000-ccache" }, > { .compatible = "sifive,fu740-c000-ccache" }, > { .compatible = "sifive,ccache0" }, > + { .compatible = "starfive,jh7110-ccache" }, > { /* end of table */ } > }; > > -- > 2.38.1 >
On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote: > Hey Emil/Hal, > > On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > This adds support for the StarFive JH7110 SoC which also > > features this SiFive cache controller. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > arch/riscv/Kconfig.socs | 1 + > > drivers/soc/Makefile | 2 +- > > drivers/soc/sifive/Kconfig | 2 +- > > drivers/soc/sifive/sifive_ccache.c | 1 + > > 4 files changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > index 69774bb362d6..5a40e05f8cab 100644 > > --- a/arch/riscv/Kconfig.socs > > +++ b/arch/riscv/Kconfig.socs > > @@ -22,6 +22,7 @@ config SOC_STARFIVE > > bool "StarFive SoCs" > > select PINCTRL > > select RESET_CONTROLLER > > + select SIFIVE_CCACHE > > Please no. I am trying to get rid of these selects + I cannot figure out > why this driver is so important that you *need* to select it. Surely the > SoC is useable without it> > Is this a hang over from your vendor tree that uses the driver to do > non-coherent stuff for the jh7100? I have tested that the board can successfully boot up without the cache driver. The `select` can be removed for JH7110. @Emil, what do you think of this? > > > select SIFIVE_PLIC > > help > > This enables support for StarFive SoC platform hardware. > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > > index 69ba6508cf2c..534669840858 100644 > > --- a/drivers/soc/Makefile > > +++ b/drivers/soc/Makefile > > @@ -26,7 +26,7 @@ obj-y += qcom/ > > obj-y += renesas/ > > obj-y += rockchip/ > > obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > > -obj-$(CONFIG_SOC_SIFIVE) += sifive/ > > +obj-y += sifive/ > > This bit is fine. > > > obj-y += sunxi/ > > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > > obj-y += ti/ > > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > > index ed4c571f8771..e86870be34c9 100644 > > --- a/drivers/soc/sifive/Kconfig > > +++ b/drivers/soc/sifive/Kconfig > > @@ -1,6 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0 > > > > -if SOC_SIFIVE > > +if SOC_SIFIVE || SOC_STARFIVE > > As I suppose is this - but hardly scalable. I suppose it doesn't really > matter. > > > config SIFIVE_CCACHE > > bool "Sifive Composable Cache controller" > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > > index 1c171150e878..9489d1a90fbc 100644 > > --- a/drivers/soc/sifive/sifive_ccache.c > > +++ b/drivers/soc/sifive/sifive_ccache.c > > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { > > { .compatible = "sifive,fu540-c000-ccache" }, > > { .compatible = "sifive,fu740-c000-ccache" }, > > { .compatible = "sifive,ccache0" }, > > + { .compatible = "starfive,jh7110-ccache" }, > > Per my second reply to the previous patch, I am not sure why you do not > just have a fallback compatible in the binding/dt for the fu740 ccache > since you appear to have identical configuration? Yeah, I will use the compatible of fu740 and modify this patch. Best regards, Hal
On Sat, 19 Nov 2022 01:32:10 +0800, Emil Renner Berthing wrote: > On Fri, 18 Nov 2022 at 02:17, Hal Feng <hal.feng@starfivetech.com> wrote: > > > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > This adds support for the StarFive JH7110 SoC which also > > features this SiFive cache controller. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > I'm fine with this, but it would be great if you could add the jh7100 > support at the same time like the original patch did. I think this patch series should only add support for JH7110. Maybe we can make a new patch series to do this. Best regards, Hal
On Tue, 22 Nov 2022 at 10:03, Hal Feng <hal.feng@starfivetech.com> wrote: > > On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote: > > Hey Emil/Hal, > > > > On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote: > > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > > > This adds support for the StarFive JH7110 SoC which also > > > features this SiFive cache controller. > > > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > > --- > > > arch/riscv/Kconfig.socs | 1 + > > > drivers/soc/Makefile | 2 +- > > > drivers/soc/sifive/Kconfig | 2 +- > > > drivers/soc/sifive/sifive_ccache.c | 1 + > > > 4 files changed, 4 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > > index 69774bb362d6..5a40e05f8cab 100644 > > > --- a/arch/riscv/Kconfig.socs > > > +++ b/arch/riscv/Kconfig.socs > > > @@ -22,6 +22,7 @@ config SOC_STARFIVE > > > bool "StarFive SoCs" > > > select PINCTRL > > > select RESET_CONTROLLER > > > + select SIFIVE_CCACHE > > > > Please no. I am trying to get rid of these selects + I cannot figure out > > why this driver is so important that you *need* to select it. Surely the > > SoC is useable without it> > > Is this a hang over from your vendor tree that uses the driver to do > > non-coherent stuff for the jh7100? > > I have tested that the board can successfully boot up without the cache > driver. The `select` can be removed for JH7110. @Emil, what do you think > of this? Yes, for the JH7110 this is not strictly needed, just like the Unmatched board. For the StarFive JH7100 it is though. So if you're only adding support for the JH7110 then it's not needed. > > > > > select SIFIVE_PLIC > > > help > > > This enables support for StarFive SoC platform hardware. > > > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > > > index 69ba6508cf2c..534669840858 100644 > > > --- a/drivers/soc/Makefile > > > +++ b/drivers/soc/Makefile > > > @@ -26,7 +26,7 @@ obj-y += qcom/ > > > obj-y += renesas/ > > > obj-y += rockchip/ > > > obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > > > -obj-$(CONFIG_SOC_SIFIVE) += sifive/ > > > +obj-y += sifive/ > > > > This bit is fine. > > > > > obj-y += sunxi/ > > > obj-$(CONFIG_ARCH_TEGRA) += tegra/ > > > obj-y += ti/ > > > diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig > > > index ed4c571f8771..e86870be34c9 100644 > > > --- a/drivers/soc/sifive/Kconfig > > > +++ b/drivers/soc/sifive/Kconfig > > > @@ -1,6 +1,6 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > > > > -if SOC_SIFIVE > > > +if SOC_SIFIVE || SOC_STARFIVE > > > > As I suppose is this - but hardly scalable. I suppose it doesn't really > > matter. > > > > > config SIFIVE_CCACHE > > > bool "Sifive Composable Cache controller" > > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > > > index 1c171150e878..9489d1a90fbc 100644 > > > --- a/drivers/soc/sifive/sifive_ccache.c > > > +++ b/drivers/soc/sifive/sifive_ccache.c > > > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { > > > { .compatible = "sifive,fu540-c000-ccache" }, > > > { .compatible = "sifive,fu740-c000-ccache" }, > > > { .compatible = "sifive,ccache0" }, > > > + { .compatible = "starfive,jh7110-ccache" }, > > > > Per my second reply to the previous patch, I am not sure why you do not > > just have a fallback compatible in the binding/dt for the fu740 ccache > > since you appear to have identical configuration? > > Yeah, I will use the compatible of fu740 and modify this patch. No, the JH7110 should not pretend to be a fu740, but if you add compatible = "starfive,jh7110-ccache", "sifive,ccache0"; then this driver should still match "sifive,ccache0" without adding the "starfive,jh7110-ccache" entry. > > Best regards, > Hal
On Tue, Nov 22, 2022 at 10:54:34AM +0100, Emil Renner Berthing wrote: > On Tue, 22 Nov 2022 at 10:03, Hal Feng <hal.feng@starfivetech.com> wrote: > > On Fri, 18 Nov 2022 19:45:57 +0800, Conor Dooley wrote: > > > Hey Emil/Hal, > > > On Fri, Nov 18, 2022 at 09:17:11AM +0800, Hal Feng wrote: > > > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > > > index 69774bb362d6..5a40e05f8cab 100644 > > > > --- a/arch/riscv/Kconfig.socs > > > > +++ b/arch/riscv/Kconfig.socs > > > > @@ -22,6 +22,7 @@ config SOC_STARFIVE > > > > bool "StarFive SoCs" > > > > select PINCTRL > > > > select RESET_CONTROLLER > > > > + select SIFIVE_CCACHE > > > > > > Please no. I am trying to get rid of these selects + I cannot figure out > > > why this driver is so important that you *need* to select it. Surely the > > > SoC is useable without it> > > > Is this a hang over from your vendor tree that uses the driver to do > > > non-coherent stuff for the jh7100? > > > > I have tested that the board can successfully boot up without the cache > > driver. The `select` can be removed for JH7110. @Emil, what do you think > > of this? > > Yes, for the JH7110 this is not strictly needed, just like the > Unmatched board. For the StarFive JH7100 it is though. > So if you're only adding support for the JH7110 then it's not needed. Even for the JH7100 there are other ways to do this than selects in arch/riscv - for example config SIFIVE_CCACHE default SOC_STARFIVE But you don't need that either if you're not adding the JH7100 :) > > > > config SIFIVE_CCACHE > > > > bool "Sifive Composable Cache controller" > > > > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c > > > > index 1c171150e878..9489d1a90fbc 100644 > > > > --- a/drivers/soc/sifive/sifive_ccache.c > > > > +++ b/drivers/soc/sifive/sifive_ccache.c > > > > @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { > > > > { .compatible = "sifive,fu540-c000-ccache" }, > > > > { .compatible = "sifive,fu740-c000-ccache" }, > > > > { .compatible = "sifive,ccache0" }, > > > > + { .compatible = "starfive,jh7110-ccache" }, > > > > > > Per my second reply to the previous patch, I am not sure why you do not > > > just have a fallback compatible in the binding/dt for the fu740 ccache > > > since you appear to have identical configuration? > > > > Yeah, I will use the compatible of fu740 and modify this patch. > > No, the JH7110 should not pretend to be a fu740, but if you add > > compatible = "starfive,jh7110-ccache", "sifive,ccache0"; > > then this driver should still match "sifive,ccache0" without adding > the "starfive,jh7110-ccache" entry. Either works for me :) If you go for "sifive,ccache0", just make sure to add the correct property enforcement - you can just copy the fu740 by the looks of things (although that'd imply that it is compatible and can fall back to it...) Thanks, Conor.
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..5a40e05f8cab 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,7 @@ config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL select RESET_CONTROLLER + select SIFIVE_CCACHE select SIFIVE_PLIC help This enables support for StarFive SoC platform hardware. diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 69ba6508cf2c..534669840858 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -26,7 +26,7 @@ obj-y += qcom/ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ -obj-$(CONFIG_SOC_SIFIVE) += sifive/ +obj-y += sifive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index ed4c571f8771..e86870be34c9 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -if SOC_SIFIVE +if SOC_SIFIVE || SOC_STARFIVE config SIFIVE_CCACHE bool "Sifive Composable Cache controller" diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 1c171150e878..9489d1a90fbc 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -107,6 +107,7 @@ static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, { .compatible = "sifive,ccache0" }, + { .compatible = "starfive,jh7110-ccache" }, { /* end of table */ } };