diff mbox series

[v5,1/1] RISC-V: Add support for XCVbi extension in CV32E40P

Message ID 20240108131456.803003-2-mary.bennett@embecosm.com
State Unresolved
Headers
Series RISC-V: Support CORE-V XCVBI extension |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Mary Bennett Jan. 8, 2024, 1:14 p.m. UTC 
  Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

gcc/ChangeLog:
	* common/config/riscv/riscv-common.cc: Create XCVbi extension
	  support.
	* config/riscv/riscv.opt: Likewise.
	* config/riscv/corev.md: Implement cv_branch<mode> pattern
	  for cv.beqimm and cv.bneimm.
	* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
	  branch instruction pattern.
	* config/riscv/constraints.md: Implement constraints
	  cv_bi_s5 - signed 5-bit immediate.
	* config/riscv/predicates.md: Implement predicate
	  const_int5s_operand - signed 5 bit immediate.
	* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
	* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
	* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
	* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
	* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc       |  2 +
 gcc/config/riscv/constraints.md               |  6 +++
 gcc/config/riscv/corev.md                     | 37 ++++++++++++++
 gcc/config/riscv/predicates.md                |  4 ++
 gcc/config/riscv/riscv.md                     |  2 +-
 gcc/config/riscv/riscv.opt                    |  2 +
 gcc/doc/sourcebuild.texi                      |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++++++++++++++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++++++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++++++++++++++++++
 gcc/testsuite/lib/target-supports.exp         | 13 +++++
 12 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

Comments

Jeff Law Jan. 9, 2024, 6:43 p.m. UTC | #1 
On 1/8/24 06:14, Mary Bennett wrote:
> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
> 
> Contributors:
>    Mary Bennett <mary.bennett@embecosm.com>
>    Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>    Pietra Ferreira <pietra.ferreira@embecosm.com>
>    Charlie Keaney
>    Jessica Mills
>    Craig Blackmore <craig.blackmore@embecosm.com>
>    Simon Cook <simon.cook@embecosm.com>
>    Jeremy Bennett <jeremy.bennett@embecosm.com>
>    Helene Chelin <helene.chelin@embecosm.com>
> 
> gcc/ChangeLog:
> 	* common/config/riscv/riscv-common.cc: Create XCVbi extension
> 	  support.
> 	* config/riscv/riscv.opt: Likewise.
> 	* config/riscv/corev.md: Implement cv_branch<mode> pattern
> 	  for cv.beqimm and cv.bneimm.
> 	* config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
> 	  branch instruction pattern.
> 	* config/riscv/constraints.md: Implement constraints
> 	  cv_bi_s5 - signed 5-bit immediate.
> 	* config/riscv/predicates.md: Implement predicate
> 	  const_int5s_operand - signed 5 bit immediate.
> 	* doc/sourcebuild.texi: Add XCVbi documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> 	* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> 	* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> 	* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> 	* lib/target-supports.exp: Add proc for XCVbi.
Assuming this has gone through a testing cycle, this is fine for the trunk.

Thanks,
jeff
Mary Bennett Jan. 22, 2024, 1:30 p.m. UTC | #2 
On 09/01/2024 18:43, Jeff Law wrote:
>
>
> On 1/8/24 06:14, Mary Bennett wrote:
>> Spec: 
>> github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>>
>> Contributors:
>>    Mary Bennett <mary.bennett@embecosm.com>
>>    Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>>    Pietra Ferreira <pietra.ferreira@embecosm.com>
>>    Charlie Keaney
>>    Jessica Mills
>>    Craig Blackmore <craig.blackmore@embecosm.com>
>>    Simon Cook <simon.cook@embecosm.com>
>>    Jeremy Bennett <jeremy.bennett@embecosm.com>
>>    Helene Chelin <helene.chelin@embecosm.com>
>>
>> gcc/ChangeLog:
>>     * common/config/riscv/riscv-common.cc: Create XCVbi extension
>>       support.
>>     * config/riscv/riscv.opt: Likewise.
>>     * config/riscv/corev.md: Implement cv_branch<mode> pattern
>>       for cv.beqimm and cv.bneimm.
>>     * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
>>       branch instruction pattern.
>>     * config/riscv/constraints.md: Implement constraints
>>       cv_bi_s5 - signed 5-bit immediate.
>>     * config/riscv/predicates.md: Implement predicate
>>       const_int5s_operand - signed 5 bit immediate.
>>     * doc/sourcebuild.texi: Add XCVbi documentation.
>>
>> gcc/testsuite/ChangeLog:
>>     * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>>     * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>>     * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>>     * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>>     * lib/target-supports.exp: Add proc for XCVbi.
> Assuming this has gone through a testing cycle, this is fine for the 
> trunk.
>
> Thanks,
> jeff

This patch passes regression. Are there any other changes required 
before it can be merged?


Kind regards,

Mary
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 0301d170a41..d61164a42b9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -355,6 +355,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1730,6 +1731,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xcvmac",        &gcc_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",        &gcc_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",        &gcc_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi",         &gcc_options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",      &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index ee1c12b2e51..e4bfa227a2f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -262,3 +262,9 @@ 
   (and (match_code "const_int")
        (and (match_test "IN_RANGE (ival, 0, 1073741823)")
             (match_test "exact_log2 (ival + 1) != -1"))))
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index adad2409fb6..66e0e998e41 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,40 @@ 
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Instructions
+(define_insn "*cv_branch<mode>"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 1 "equality_operator"
+			 [(match_operand:X 2 "register_operand" "r")
+			  (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  "TARGET_XCVBI"
+{
+  if (get_attr_length (insn) == 12)
+    return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+  return "cv.b%C1imm\t%2,%3,%0";
+}
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
+
+(define_insn "*branch<mode>"
+  [(set (pc)
+        (if_then_else
+         (match_operator 1 "ordered_comparison_operator"
+                         [(match_operand:X 2 "register_operand" "r")
+                          (match_operand:X 3 "reg_or_0_operand" "rJ")])
+         (label_ref (match_operand 0 "" ""))
+         (pc)))]
+  "TARGET_XCVBI"
+{
+  if (get_attr_length (insn) == 12)
+    return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+  return "b%C1\t%2,%z3,%l0";
+}
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index b1a79cae50a..26a67ddf628 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -425,6 +425,10 @@ 
   (ior (match_operand 0 "register_operand")
        (match_code "const_int")))
 
+(define_predicate "const_int5s_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
+
 ;; Predicates for the V extension.
 (define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..5b7bae1ce71 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2732,7 +2732,7 @@ 
 			  (match_operand:X 3 "reg_or_0_operand" "rJ")])
 	 (label_ref (match_operand 0 "" ""))
 	 (pc)))]
-  ""
+  "!TARGET_XCVBI"
 {
   if (get_attr_length (insn) == 12)
     return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 44ed6d69da2..d51027350af 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -425,6 +425,8 @@  Mask(XCVALU) Var(riscv_xcv_subext)
 
 Mask(XCVELW) Var(riscv_xcv_subext)
 
+Mask(XCVBI) Var(riscv_xcv_subext)
+
 TargetVariable
 int riscv_xthead_subext
 
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 3a394e7739b..130a6d964e3 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2505,6 +2505,9 @@  Test system has support for the CORE-V ALU extension.
 @item cv_elw
 Test system has support for the CORE-V ELW extension.
 
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
 @end table
 
 @subsubsection Other hardware attributes
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
new file mode 100644
index 00000000000..5b6ba5b8ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 12);
+    return a != 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
new file mode 100644
index 00000000000..bb2e5843957
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
@@ -0,0 +1,48 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != -16 ? x : y;
+}
+
+int
+foo2 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 0 ? x : y;
+}
+
+int
+foo3 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 15 ? x : y;
+}
+
+int
+foo4 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != -17 ? x : y;
+}
+
+int
+foo5 (int a, int x, int y)
+{
+    a = __builtin_expect (a, 10);
+    return a != 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.beqimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "beq\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
new file mode 100644
index 00000000000..21eab38a08d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1(int a, int x, int y)
+{
+    a = __builtin_expect(a, 10);
+    return a == 10 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),10,\(\?\:.L\[0-9\]\)" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
new file mode 100644
index 00000000000..a028f684489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
@@ -0,0 +1,48 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target cv_bi } */
+/* { dg-options "-march=rv32i_xcvbi -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* }  { "-O0" } { "" } } */
+
+/* __builtin_expect is used to provide the compiler with
+   branch prediction information and to direct the compiler
+   to the expected flow through the code.  */
+
+int
+foo1(int a, int x, int y)
+{
+    a = __builtin_expect(a, -16);
+    return a == -16 ? x : y;
+}
+
+int
+foo2(int a, int x, int y)
+{
+    a = __builtin_expect(a, 0);
+    return a == 0 ? x : y;
+}
+
+int
+foo3(int a, int x, int y)
+{
+    a = __builtin_expect(a, 15);
+    return a == 15 ? x : y;
+}
+
+int
+foo4(int a, int x, int y)
+{
+    a = __builtin_expect(a, -17);
+    return a == -17 ? x : y;
+}
+
+int
+foo5(int a, int x, int y)
+{
+    a = __builtin_expect(a, 16);
+    return a == 16 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),-16,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),0,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "cv\\.bneimm\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),15,\(\?\:.L\[0-9\]\)" 1 } } */
+/* { dg-final { scan-assembler-times "bne\t\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:t\[0-6\]\|a\[0-7\]\|s\[1-11\]\),\(\?\:.L\[0-9\]+\)" 2 } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b27c30b8c51..8d90aa15c95 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -13314,6 +13314,19 @@  proc check_effective_target_cv_elw { } {
     } "-march=rv32i_xcvelw" ]
 }
 
+# Return 1 if the CORE-V BI extension is available
+proc check_effective_target_cv_bi { } {
+    if { !([istarget riscv*-*-*]) } {
+         return 0
+     }
+    return [check_no_compiler_messages cv_bi object {
+        void foo (void)
+        {
+          asm ("cv.beqimm t0, -16, foo");
+        }
+    } "-march=rv32i_xcvbi" ]
+}
+
 proc check_effective_target_loongarch_sx { } {
     return [check_no_compiler_messages loongarch_lsx assembly {
        #if !defined(__loongarch_sx)