diff mbox series

[2/2] arm: Add cortex-m52 doc

Message ID 0c5c7a33-93c9-46ad-85f3-b6f4bb3d5ddd@gmail.com
State Accepted
Headers
Series [1/2] arm: Add cortex-m52 core |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Chung-Ju Wu Jan. 8, 2024, 6:16 a.m. UTC 
  Hi,

This is the patch to add cortex-m52 in the Arm-related options
sections of the gcc invoke.texi documentation.

Is it OK for trunk?

Regards,
jasonwucj
From b7ce3d499d4bf087ec54a5f834876c9108d46c3d Mon Sep 17 00:00:00 2001
From: Chung-Ju Wu <jasonwucj@gmail.com>
Date: Thu, 7 Dec 2023 11:26:25 +0800
Subject: [PATCH 2/2] arm: Add Arm Cortex-M52 CPU documentation.

Signed-off-by: Chung-Ju Wu <jasonwucj@gmail.com>

gcc/ChangeLog:

	* doc/invoke.texi: Update docs.
---
 gcc/doc/invoke.texi | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Comments

Kyrylo Tkachov Jan. 8, 2024, 2:32 p.m. UTC | #1 
> -----Original Message-----
> From: Chung-Ju Wu <jasonwucj@gmail.com>
> Sent: Monday, January 8, 2024 6:17 AM
> To: gcc-patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>
> Cc: Jason.Wu@anshingtek.com.tw
> Subject: [PATCH 2/2] arm: Add cortex-m52 doc
> 
> Hi,
> 
> This is the patch to add cortex-m52 in the Arm-related options
> sections of the gcc invoke.texi documentation.
> 
> Is it OK for trunk?

In the ChangeLog entry:
gcc/ChangeLog:

	* doc/invoke.texi: Update docs.

Let's be more specific and specify something like
	* doc/invoke.texi (Arm Options): Document Cortex-m52 options.

Ok with a better ChangeLog entry.
Thanks,
Kyrill


> 
> Regards,
> jasonwucj
Chung-Ju Wu Jan. 9, 2024, 7:23 a.m. UTC | #2 
On 2024/01/08 22:32 UTC+8, Kyrylo Tkachov wrote:
> 
> 
>> -----Original Message-----
>> From: Chung-Ju Wu <jasonwucj@gmail.com>
>> Sent: Monday, January 8, 2024 6:17 AM
>> To: gcc-patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
>> <Kyrylo.Tkachov@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>
>> Cc: Jason.Wu@anshingtek.com.tw
>> Subject: [PATCH 2/2] arm: Add cortex-m52 doc
>>
>> Hi,
>>
>> This is the patch to add cortex-m52 in the Arm-related options
>> sections of the gcc invoke.texi documentation.
>>
>> Is it OK for trunk?
> 
> In the ChangeLog entry:
> gcc/ChangeLog:
> 
> 	* doc/invoke.texi: Update docs.
> 
> Let's be more specific and specify something like
> 	* doc/invoke.texi (Arm Options): Document Cortex-m52 options.
> 
> Ok with a better ChangeLog entry.

Hi Kyrylo,

Thanks for the suggestion and approval.
The patch is revised and committed as: https://gcc.gnu.org/g:43c4f982113076ad54c3405f865cc63b0a5ba5aa

Thanks,
jasonwucj


> Thanks,
> Kyrill
>>
>> Regards,
>> jasonwucj
diff mbox series

Patch

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d71583853f0..bdbe0074cb4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23094,7 +23094,7 @@  Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
-@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
+@samp{cortex-m35p}, @samp{cortex-m52}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1},
 @samp{cortex-x1c}, @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale},
@@ -23160,34 +23160,34 @@  The following extension options are common to the listed CPUs:
 @table @samp
 @item +nodsp
 Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p},
-@samp{cortex-m55} and @samp{cortex-m85}. Also disable the M-Profile Vector
-Extension (MVE) integer and single precision floating-point instructions on
-@samp{cortex-m55} and @samp{cortex-m85}.
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
+Also disable the M-Profile Vector Extension (MVE) integer and
+single precision floating-point instructions on
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +nopacbti
 Disable the Pointer Authentication and Branch Target Identification Extension
-on @samp{cortex-m85}.
+on @samp{cortex-m52} and @samp{cortex-m85}.
 
 @item +nomve
 Disable the M-Profile Vector Extension (MVE) integer and single precision
-floating-point instructions on @samp{cortex-m55} and @samp{cortex-m85}.
+floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +nomve.fp
 Disable the M-Profile Vector Extension (MVE) single precision floating-point
-instructions on @samp{cortex-m55} and @samp{cortex-m85}.
+instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
-to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} and @samp{cortex-m55}.
 
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},
 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
 @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
 @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p}
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33}, @samp{cortex-m35p},
-@samp{cortex-m55} and @samp{cortex-m85}.
+@samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.
 Disables the floating-point and SIMD instructions on
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
@@ -23530,9 +23530,9 @@  Development Tools Engineering Specification", which can be found on
 Mitigate against a potential security issue with the @code{VLLDM} instruction
 in some M-profile devices when using CMSE (CVE-2021-365465).  This option is
 enabled by default when the option @option{-mcpu=} is used with
-@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55}, @code{cortex-m85}
-or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465} can be used
-to disable the mitigation.
+@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m52}, @code{cortex-m55},
+@code{cortex-m85} or @code{star-mc1}. The option @option{-mno-fix-cmse-cve-2021-35465}
+can be used to disable the mitigation.
 
 @opindex mstack-protector-guard
 @opindex mstack-protector-guard-offset