diff mbox series

[v2,2/2] clk: mediatek: add infracfg reset controller for mt7988

Message ID 20240105162056.43266-3-linux@fw-web.de
State New
Headers
Series Add reset controller to mt7988 infracfg |

Commit Message

Frank Wunderlich Jan. 5, 2024, 4:20 p.m. UTC 
  From: Frank Wunderlich <frank-w@public-files.de>

Infracfg can also operate as reset controller, add support for it.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

AngeloGioacchino Del Regno Jan. 8, 2024, 10:12 a.m. UTC | #1 
Il 05/01/24 17:20, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w@public-files.de>
> 
> Infracfg can also operate as reset controller, add support for it.
> 
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
>   drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> index 8011ef278bea..1660a45349ff 100644
> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> @@ -14,6 +14,9 @@
>   #include "clk-gate.h"
>   #include "clk-mux.h"
>   #include <dt-bindings/clock/mediatek,mt7988-clk.h>
> +#include <dt-bindings/reset/mediatek,mt7988-resets.h>
> +
> +#define	INFRA_RST_SET_OFFSET	0x80
>   
>   static DEFINE_SPINLOCK(mt7988_clk_lock);
>   
> @@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = {
>   	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
>   };
>   
> +static u16 infra_rst_ofs[] = {
> +	INFRA_RST_SET_OFFSET,
> +};
> +
> +static u16 infra_idx_map[] = {
> +	[MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9,

The MT7988A datasheet says that INFRA_RST0 bit 9 is CONN2EMI_M0_GALS_SLV_SWRST, so
this is wrong: THERM_CTRL_SWRST is in the RST1 register, bit 9.

Also, I'm sure that you really want to add the PCIe MAC reset bit as well, to be
used with the PCIe driver...

[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,

Enjoy... :-)

Cheers,
Angelo
Frank Wunderlich Jan. 8, 2024, 1:46 p.m. UTC | #2 
Am 8. Januar 2024 11:12:26 MEZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:
>Il 05/01/24 17:20, Frank Wunderlich ha scritto:
>> From: Frank Wunderlich <frank-w@public-files.de>
>> 
>> Infracfg can also operate as reset controller, add support for it.
>> 
>> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
>> ---
>>   drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>> 
>> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
>> index 8011ef278bea..1660a45349ff 100644
>> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
>> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
>> @@ -14,6 +14,9 @@
>>   #include "clk-gate.h"
>>   #include "clk-mux.h"
>>   #include <dt-bindings/clock/mediatek,mt7988-clk.h>
>> +#include <dt-bindings/reset/mediatek,mt7988-resets.h>
>> +
>> +#define	INFRA_RST_SET_OFFSET	0x80
>>     static DEFINE_SPINLOCK(mt7988_clk_lock);
>>   @@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = {
>>   	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
>>   };
>>   +static u16 infra_rst_ofs[] = {
>> +	INFRA_RST_SET_OFFSET,
>> +};
>> +
>> +static u16 infra_idx_map[] = {
>> +	[MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9,
>
>The MT7988A datasheet says that INFRA_RST0 bit 9 is CONN2EMI_M0_GALS_SLV_SWRST, so
>this is wrong: THERM_CTRL_SWRST is in the RST1 register, bit 9.
>
>Also, I'm sure that you really want to add the PCIe MAC reset bit as well, to be
>used with the PCIe driver...
>
>[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
>[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,

Yes you are right...i have only rst1 as screenshot,need to get the full datasheet or can you tell me base address for rst0? Need to change value of INFRA_RST_SET_OFFSET then to rst0 and check RST_NR_PER_BANK to be correct.

>Enjoy... :-)
>
>Cheers,
>Angelo
>


regards Frank
AngeloGioacchino Del Regno Jan. 8, 2024, 2:24 p.m. UTC | #3 
Il 08/01/24 14:46, Frank Wunderlich ha scritto:
> Am 8. Januar 2024 11:12:26 MEZ schrieb AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>:
>> Il 05/01/24 17:20, Frank Wunderlich ha scritto:
>>> From: Frank Wunderlich <frank-w@public-files.de>
>>>
>>> Infracfg can also operate as reset controller, add support for it.
>>>
>>> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
>>> ---
>>>    drivers/clk/mediatek/clk-mt7988-infracfg.c | 20 ++++++++++++++++++++
>>>    1 file changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
>>> index 8011ef278bea..1660a45349ff 100644
>>> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
>>> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
>>> @@ -14,6 +14,9 @@
>>>    #include "clk-gate.h"
>>>    #include "clk-mux.h"
>>>    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
>>> +#include <dt-bindings/reset/mediatek,mt7988-resets.h>
>>> +
>>> +#define	INFRA_RST_SET_OFFSET	0x80
>>>      static DEFINE_SPINLOCK(mt7988_clk_lock);
>>>    @@ -249,12 +252,29 @@ static const struct mtk_gate infra_clks[] = {
>>>    	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
>>>    };
>>>    +static u16 infra_rst_ofs[] = {
>>> +	INFRA_RST_SET_OFFSET,
>>> +};
>>> +
>>> +static u16 infra_idx_map[] = {
>>> +	[MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9,
>>
>> The MT7988A datasheet says that INFRA_RST0 bit 9 is CONN2EMI_M0_GALS_SLV_SWRST, so
>> this is wrong: THERM_CTRL_SWRST is in the RST1 register, bit 9.
>>
>> Also, I'm sure that you really want to add the PCIe MAC reset bit as well, to be
>> used with the PCIe driver...
>>
>> [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
>> [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
> 
> Yes you are right...i have only rst1 as screenshot,need to get the full datasheet or can you tell me base address for rst0? Need to change value of INFRA_RST_SET_OFFSET then to rst0 and check RST_NR_PER_BANK to be correct.

The datasheet is public ... [1] has it in the Resources paragraph :-)

Anyway, since I already have it here in front of me...

10001070 INFRA_GLOBALCON_RST0_SET
10001080 INFRA_GLOBALCON_RST1_SET

[1]: https://wiki.banana-pi.org/Banana_Pi_BPI-R4

Cheers,
Angelo
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
index 8011ef278bea..1660a45349ff 100644
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
@@ -14,6 +14,9 @@ 
 #include "clk-gate.h"
 #include "clk-mux.h"
 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
+
+#define	INFRA_RST_SET_OFFSET	0x80
 
 static DEFINE_SPINLOCK(mt7988_clk_lock);
 
@@ -249,12 +252,29 @@  static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
 };
 
+static u16 infra_rst_ofs[] = {
+	INFRA_RST_SET_OFFSET,
+};
+
+static u16 infra_idx_map[] = {
+	[MT7988_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 9,
+};
+
+static struct mtk_clk_rst_desc infra_rst_desc = {
+	.version = MTK_RST_SET_CLR,
+	.rst_bank_ofs = infra_rst_ofs,
+	.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
+	.rst_idx_map = infra_idx_map,
+	.rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
+};
+
 static const struct mtk_clk_desc infra_desc = {
 	.clks = infra_clks,
 	.num_clks = ARRAY_SIZE(infra_clks),
 	.mux_clks = infra_muxes,
 	.num_mux_clks = ARRAY_SIZE(infra_muxes),
 	.clk_lock = &mt7988_clk_lock,
+	.rst_desc = &infra_rst_desc,
 };
 
 static const struct of_device_id of_match_clk_mt7988_infracfg[] = {