[v14,15/22] PCI: microchip: Add event irqchip field to host port and add PLDA irqchip
Commit Message
As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt
controller.
Microchip PolarFire PCIE event IRQs includes PLDA interrupts and
Polarfire their own interrupts. The interrupt irqchip ops includes
ack/mask/unmask interrupt ops, which will write correct registers.
Microchip Polarfire PCIe additional interrupts require to write Polarfire
SoC self-defined registers. So Microchip PCIe event irqchip ops can not
be re-used.
To support PLDA its own event IRQ process, implements PLDA irqchip ops and
add event irqchip field to struct pcie_plda_rp.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
drivers/pci/controller/plda/pcie-plda.h | 5 +-
2 files changed, 69 insertions(+), 2 deletions(-)
Comments
> 主题: [PATCH v14 15/22] PCI: microchip: Add event irqchip field to host port and
> add PLDA irqchip
>
> As PLDA dts binding doc(Documentation/devicetree/bindings/pci/
> plda,xpressrich3-axi-common.yaml) showes, PLDA PCIe contains an interrupt
> controller.
>
> Microchip PolarFire PCIE event IRQs includes PLDA interrupts and Polarfire their
> own interrupts. The interrupt irqchip ops includes ack/mask/unmask interrupt
> ops, which will write correct registers.
> Microchip Polarfire PCIe additional interrupts require to write Polarfire SoC
> self-defined registers. So Microchip PCIe event irqchip ops can not be re-used.
>
> To support PLDA its own event IRQ process, implements PLDA irqchip ops and
> add event irqchip field to struct pcie_plda_rp.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../pci/controller/plda/pcie-microchip-host.c | 66 ++++++++++++++++++-
> drivers/pci/controller/plda/pcie-plda.h | 5 +-
> 2 files changed, 69 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> b/drivers/pci/controller/plda/pcie-microchip-host.c
> index b3df373a2141..beaf5c27da84 100644
> --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> @@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
> .irq_unmask = mc_unmask_event_irq,
> };
>
> +static u32 plda_hwirq_to_mask(int hwirq) {
> + u32 mask;
> +
> + /* hwirq 23 - 0 are the same with register */
> + if (hwirq < EVENT_PM_MSI_INT_INTX)
> + mask = BIT(hwirq);
> + else if (hwirq == EVENT_PM_MSI_INT_INTX)
> + mask = PM_MSI_INT_INTX_MASK;
> + else
> + mask = BIT(hwirq + PCI_NUM_INTX - 1);
> +
> + return mask;
> +}
> +
Hi Tomas
plda_hwirq_to_mask () is event to register mapping.
register bit event
0 0
| |
| |
23 23
24 ----> 24 (intx)
| |
27 ---+
28 25
| |
31 28
> +static void plda_ack_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> +
> + writel_relaxed(plda_hwirq_to_mask(data->hwirq),
> + port->bridge_addr + ISTATUS_LOCAL); }
> +
> +static void plda_mask_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> + u32 mask, val;
> +
> + mask = plda_hwirq_to_mask(data->hwirq);
> +
> + raw_spin_lock(&port->lock);
> + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> + val &= ~mask;
> + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> + raw_spin_unlock(&port->lock);
> +}
> +
> +static void plda_unmask_event_irq(struct irq_data *data) {
> + struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
> + u32 mask, val;
> +
> + mask = plda_hwirq_to_mask(data->hwirq);
> +
> + raw_spin_lock(&port->lock);
> + val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
> + val |= mask;
> + writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
> + raw_spin_unlock(&port->lock);
> +}
> +
> +static struct irq_chip plda_event_irq_chip = {
> + .name = "PLDA PCIe EVENT",
> + .irq_ack = plda_ack_event_irq,
> + .irq_mask = plda_mask_event_irq,
> + .irq_unmask = plda_unmask_event_irq,
> +};
> +
> static const struct plda_event_ops plda_event_ops = {
> .get_events = plda_get_events,
> };
> @@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops =
> { static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
> irq_hw_number_t hwirq)
> {
> - irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
> + struct plda_pcie_rp *port = (void *)domain->host_data;
> +
> + irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
> irq_set_chip_data(irq, domain->host_data);
>
> return 0;
> @@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device
> *pdev,
> if (!port->event_ops)
> port->event_ops = &plda_event_ops;
>
> + if (!port->event_irq_chip)
> + port->event_irq_chip = &plda_event_irq_chip;
> +
> ret = plda_pcie_init_irq_domains(port);
> if (ret) {
> dev_err(dev, "failed creating IRQ domains\n"); @@ -1039,6 +1102,7
> @@ static int mc_platform_init(struct pci_config_window *cfg)
> return ret;
>
> port->plda.event_ops = &mc_event_ops;
> + port->plda.event_irq_chip = &mc_event_irq_chip;
>
> /* Address translation is up; safe to enable interrupts */
> ret = plda_init_interrupts(pdev, &port->plda, &mc_event); diff --git
> a/drivers/pci/controller/plda/pcie-plda.h
> b/drivers/pci/controller/plda/pcie-plda.h
> index 9db92ccf286c..a3ce01735bea 100644
> --- a/drivers/pci/controller/plda/pcie-plda.h
> +++ b/drivers/pci/controller/plda/pcie-plda.h
> @@ -107,7 +107,9 @@ enum plda_int_event {
>
> #define PLDA_NUM_DMA_EVENTS 16
>
> -#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS +
> PLDA_INT_EVENT_NUM)
> +#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS +
> PLDA_INTX)
> +#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS +
> PLDA_MSI)
> +#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS +
> PLDA_INT_EVENT_NUM)
>
> /*
> * PLDA interrupt register
> @@ -155,6 +157,7 @@ struct plda_pcie_rp {
> raw_spinlock_t lock;
> struct plda_msi msi;
> const struct plda_event_ops *event_ops;
> + const struct irq_chip *event_irq_chip;
> void __iomem *bridge_addr;
> int num_events;
> };
> --
> 2.17.1
@@ -770,6 +770,64 @@ static struct irq_chip mc_event_irq_chip = {
.irq_unmask = mc_unmask_event_irq,
};
+static u32 plda_hwirq_to_mask(int hwirq)
+{
+ u32 mask;
+
+ /* hwirq 23 - 0 are the same with register */
+ if (hwirq < EVENT_PM_MSI_INT_INTX)
+ mask = BIT(hwirq);
+ else if (hwirq == EVENT_PM_MSI_INT_INTX)
+ mask = PM_MSI_INT_INTX_MASK;
+ else
+ mask = BIT(hwirq + PCI_NUM_INTX - 1);
+
+ return mask;
+}
+
+static void plda_ack_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+
+ writel_relaxed(plda_hwirq_to_mask(data->hwirq),
+ port->bridge_addr + ISTATUS_LOCAL);
+}
+
+static void plda_mask_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+ u32 mask, val;
+
+ mask = plda_hwirq_to_mask(data->hwirq);
+
+ raw_spin_lock(&port->lock);
+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
+ val &= ~mask;
+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
+ raw_spin_unlock(&port->lock);
+}
+
+static void plda_unmask_event_irq(struct irq_data *data)
+{
+ struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
+ u32 mask, val;
+
+ mask = plda_hwirq_to_mask(data->hwirq);
+
+ raw_spin_lock(&port->lock);
+ val = readl_relaxed(port->bridge_addr + IMASK_LOCAL);
+ val |= mask;
+ writel_relaxed(val, port->bridge_addr + IMASK_LOCAL);
+ raw_spin_unlock(&port->lock);
+}
+
+static struct irq_chip plda_event_irq_chip = {
+ .name = "PLDA PCIe EVENT",
+ .irq_ack = plda_ack_event_irq,
+ .irq_mask = plda_mask_event_irq,
+ .irq_unmask = plda_unmask_event_irq,
+};
+
static const struct plda_event_ops plda_event_ops = {
.get_events = plda_get_events,
};
@@ -777,7 +835,9 @@ static const struct plda_event_ops plda_event_ops = {
static int plda_pcie_event_map(struct irq_domain *domain, unsigned int irq,
irq_hw_number_t hwirq)
{
- irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq);
+ struct plda_pcie_rp *port = (void *)domain->host_data;
+
+ irq_set_chip_and_handler(irq, port->event_irq_chip, handle_level_irq);
irq_set_chip_data(irq, domain->host_data);
return 0;
@@ -962,6 +1022,9 @@ static int plda_init_interrupts(struct platform_device *pdev,
if (!port->event_ops)
port->event_ops = &plda_event_ops;
+ if (!port->event_irq_chip)
+ port->event_irq_chip = &plda_event_irq_chip;
+
ret = plda_pcie_init_irq_domains(port);
if (ret) {
dev_err(dev, "failed creating IRQ domains\n");
@@ -1039,6 +1102,7 @@ static int mc_platform_init(struct pci_config_window *cfg)
return ret;
port->plda.event_ops = &mc_event_ops;
+ port->plda.event_irq_chip = &mc_event_irq_chip;
/* Address translation is up; safe to enable interrupts */
ret = plda_init_interrupts(pdev, &port->plda, &mc_event);
@@ -107,7 +107,9 @@ enum plda_int_event {
#define PLDA_NUM_DMA_EVENTS 16
-#define PLDA_MAX_INT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
+#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX)
+#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI)
+#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)
/*
* PLDA interrupt register
@@ -155,6 +157,7 @@ struct plda_pcie_rp {
raw_spinlock_t lock;
struct plda_msi msi;
const struct plda_event_ops *event_ops;
+ const struct irq_chip *event_irq_chip;
void __iomem *bridge_addr;
int num_events;
};