LoongArch: Add sign_extend pattern for 32-bit rotate shift
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Commit Message
Remove a redundant sign extension.
gcc/ChangeLog:
* config/loongarch/loongarch.md (rotrsi3_extend): New
define_insn.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/rotrw.c: New test.
---
Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk?
gcc/config/loongarch/loongarch.md | 10 ++++++++++
gcc/testsuite/gcc.target/loongarch/rotrw.c | 17 +++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/rotrw.c
Comments
LGTM!
Thanks!
在 2023/12/17 下午11:16, Xi Ruoyao 写道:
> Remove a redundant sign extension.
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch.md (rotrsi3_extend): New
> define_insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/loongarch/rotrw.c: New test.
> ---
>
> Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk?
>
> gcc/config/loongarch/loongarch.md | 10 ++++++++++
> gcc/testsuite/gcc.target/loongarch/rotrw.c | 17 +++++++++++++++++
> 2 files changed, 27 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/loongarch/rotrw.c
>
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index c7058282a21..30025bf1908 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -2893,6 +2893,16 @@ (define_insn "rotr<mode>3"
> [(set_attr "type" "shift,shift")
> (set_attr "mode" "<MODE>")])
>
> +(define_insn "rotrsi3_extend"
> + [(set (match_operand:DI 0 "register_operand" "=r,r")
> + (sign_extend:DI
> + (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
> + (match_operand:SI 2 "arith_operand" "r,I"))))]
> + "TARGET_64BIT"
> + "rotr%i2.w\t%0,%1,%2"
> + [(set_attr "type" "shift,shift")
> + (set_attr "mode" "SI")])
> +
> ;; The following templates were added to generate "bstrpick.d + alsl.d"
> ;; instruction pairs.
> ;; It is required that the values of const_immalsl_operand and
> diff --git a/gcc/testsuite/gcc.target/loongarch/rotrw.c b/gcc/testsuite/gcc.target/loongarch/rotrw.c
> new file mode 100644
> index 00000000000..6ed45e8b86c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/rotrw.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +/* { dg-final { scan-assembler "rotr\\.w\t\\\$r4,\\\$r4,\\\$r5" } } */
> +/* { dg-final { scan-assembler "rotri\\.w\t\\\$r4,\\\$r4,5" } } */
> +/* { dg-final { scan-assembler-not "slli\\.w" } } */
> +
> +unsigned
> +rotr (unsigned a, unsigned b)
> +{
> + return a >> b | a << 32 - b;
> +}
> +
> +unsigned
> +rotri (unsigned a)
> +{
> + return a >> 5 | a << 27;
> +}
@@ -2893,6 +2893,16 @@ (define_insn "rotr<mode>3"
[(set_attr "type" "shift,shift")
(set_attr "mode" "<MODE>")])
+(define_insn "rotrsi3_extend"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+ (sign_extend:DI
+ (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
+ (match_operand:SI 2 "arith_operand" "r,I"))))]
+ "TARGET_64BIT"
+ "rotr%i2.w\t%0,%1,%2"
+ [(set_attr "type" "shift,shift")
+ (set_attr "mode" "SI")])
+
;; The following templates were added to generate "bstrpick.d + alsl.d"
;; instruction pairs.
;; It is required that the values of const_immalsl_operand and
new file mode 100644
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "rotr\\.w\t\\\$r4,\\\$r4,\\\$r5" } } */
+/* { dg-final { scan-assembler "rotri\\.w\t\\\$r4,\\\$r4,5" } } */
+/* { dg-final { scan-assembler-not "slli\\.w" } } */
+
+unsigned
+rotr (unsigned a, unsigned b)
+{
+ return a >> b | a << 32 - b;
+}
+
+unsigned
+rotri (unsigned a)
+{
+ return a >> 5 | a << 27;
+}