diff mbox series

arm64: dts: qcom: x1e80100: align mem timer size cells with bindings

Message ID 20231218150656.72892-1-krzysztof.kozlowski@linaro.org
State New
Headers
Series arm64: dts: qcom: x1e80100: align mem timer size cells with bindings |

Commit Message

Krzysztof Kozlowski Dec. 18, 2023, 3:06 p.m. UTC 
  The ARMv7 memory mapped architected timer bindings expect MMIO sizes up
to 32-bit.  Keep 64-bit addressing but change the size of memory mapping
to 32-bit (size-cells=1) and adjust the ranges to match this.

This fixes dtbs_check warnings like:

  x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected

Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

Comments

Konrad Dybcio Dec. 18, 2023, 3:12 p.m. UTC | #1 
On 18.12.2023 16:06, Krzysztof Kozlowski wrote:
> The ARMv7 memory mapped architected timer bindings expect MMIO sizes up
> to 32-bit.  Keep 64-bit addressing but change the size of memory mapping
> to 32-bit (size-cells=1) and adjust the ranges to match this.
> 
> This fixes dtbs_check warnings like:
> 
>   x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected
> 
> Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
Abel Vesa Dec. 19, 2023, 7:13 a.m. UTC | #2 
On 23-12-18 16:06:56, Krzysztof Kozlowski wrote:
> The ARMv7 memory mapped architected timer bindings expect MMIO sizes up
> to 32-bit.  Keep 64-bit addressing but change the size of memory mapping
> to 32-bit (size-cells=1) and adjust the ranges to match this.
> 
> This fixes dtbs_check warnings like:
> 
>   x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected
> 
> Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index fd09fbc7d8e7..be1285d9919e 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3417,12 +3417,12 @@ timer@17800000 {
>  			reg = <0 0x17800000 0 0x1000>;
>  
>  			#address-cells = <2>;
> -			#size-cells = <2>;
> -			ranges;
> +			#size-cells = <1>;
> +			ranges = <0 0 0 0 0x20000000>;
>  
>  			frame@17801000 {
> -				reg = <0 0x17801000 0 0x1000>,
> -				      <0 0x17802000 0 0x1000>;
> +				reg = <0 0x17801000 0x1000>,
> +				      <0 0x17802000 0x1000>;
>  
>  				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> @@ -3431,7 +3431,7 @@ frame@17801000 {
>  			};
>  
>  			frame@17803000 {
> -				reg = <0 0x17803000 0 0x1000>;
> +				reg = <0 0x17803000 0x1000>;
>  
>  				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>  
> @@ -3441,7 +3441,7 @@ frame@17803000 {
>  			};
>  
>  			frame@17805000 {
> -				reg = <0 0x17805000 0 0x1000>;
> +				reg = <0 0x17805000 0x1000>;
>  
>  				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>  
> @@ -3451,7 +3451,7 @@ frame@17805000 {
>  			};
>  
>  			frame@17807000 {
> -				reg = <0 0x17807000 0 0x1000>;
> +				reg = <0 0x17807000 0x1000>;
>  
>  				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>  
> @@ -3461,7 +3461,7 @@ frame@17807000 {
>  			};
>  
>  			frame@17809000 {
> -				reg = <0 0x17809000 0 0x1000>;
> +				reg = <0 0x17809000 0x1000>;
>  
>  				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>  
> @@ -3471,7 +3471,7 @@ frame@17809000 {
>  			};
>  
>  			frame@1780b000 {
> -				reg = <0 0x1780b000 0 0x1000>;
> +				reg = <0 0x1780b000 0x1000>;
>  
>  				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>  
> @@ -3481,7 +3481,7 @@ frame@1780b000 {
>  			};
>  
>  			frame@1780d000 {
> -				reg = <0 0x1780d000 0 0x1000>;
> +				reg = <0 0x1780d000 0x1000>;
>  
>  				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>  
> -- 
> 2.34.1
>
Bjorn Andersson Dec. 19, 2023, 7:33 p.m. UTC | #3 
On Mon, 18 Dec 2023 16:06:56 +0100, Krzysztof Kozlowski wrote:
> The ARMv7 memory mapped architected timer bindings expect MMIO sizes up
> to 32-bit.  Keep 64-bit addressing but change the size of memory mapping
> to 32-bit (size-cells=1) and adjust the ranges to match this.
> 
> This fixes dtbs_check warnings like:
> 
>   x1e80100-qcp.dtb: timer@17800000: #size-cells:0:0: 1 was expected
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: x1e80100: align mem timer size cells with bindings
      commit: d336355492e4ab8c1fd78e582077146e065d1924

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index fd09fbc7d8e7..be1285d9919e 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3417,12 +3417,12 @@  timer@17800000 {
 			reg = <0 0x17800000 0 0x1000>;
 
 			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
+			#size-cells = <1>;
+			ranges = <0 0 0 0 0x20000000>;
 
 			frame@17801000 {
-				reg = <0 0x17801000 0 0x1000>,
-				      <0 0x17802000 0 0x1000>;
+				reg = <0 0x17801000 0x1000>,
+				      <0 0x17802000 0x1000>;
 
 				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -3431,7 +3431,7 @@  frame@17801000 {
 			};
 
 			frame@17803000 {
-				reg = <0 0x17803000 0 0x1000>;
+				reg = <0 0x17803000 0x1000>;
 
 				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3441,7 +3441,7 @@  frame@17803000 {
 			};
 
 			frame@17805000 {
-				reg = <0 0x17805000 0 0x1000>;
+				reg = <0 0x17805000 0x1000>;
 
 				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3451,7 +3451,7 @@  frame@17805000 {
 			};
 
 			frame@17807000 {
-				reg = <0 0x17807000 0 0x1000>;
+				reg = <0 0x17807000 0x1000>;
 
 				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3461,7 +3461,7 @@  frame@17807000 {
 			};
 
 			frame@17809000 {
-				reg = <0 0x17809000 0 0x1000>;
+				reg = <0 0x17809000 0x1000>;
 
 				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3471,7 +3471,7 @@  frame@17809000 {
 			};
 
 			frame@1780b000 {
-				reg = <0 0x1780b000 0 0x1000>;
+				reg = <0 0x1780b000 0x1000>;
 
 				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3481,7 +3481,7 @@  frame@1780b000 {
 			};
 
 			frame@1780d000 {
-				reg = <0 0x1780d000 0 0x1000>;
+				reg = <0 0x1780d000 0x1000>;
 
 				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;