[v7,14/14] dt-bindings: net: ar803x: add qca8084 PHY propetry
Commit Message
The following properties are added for qca8084 PHY.
1. add the compatible string "ethernet-phy-id004d.d180" since
the PHY device is not accessible during MDIO bus register.
2. add property "qcom,phy-addr-fixup" for customizing MDIO address.
3. add property "qcom,phy-work-mode" for specifying qca8084 PHY
work mode.
4. add the initial clocks and resets.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
.../devicetree/bindings/net/qca,ar803x.yaml | 158 +++++++++++++++++-
1 file changed, 155 insertions(+), 3 deletions(-)
Comments
On 14/12/2023 10:48, Luo Jie wrote:
> The following properties are added for qca8084 PHY.
>
> 1. add the compatible string "ethernet-phy-id004d.d180" since
> the PHY device is not accessible during MDIO bus register.
> 2. add property "qcom,phy-addr-fixup" for customizing MDIO address.
Why? Commit msg must explain why, not "what".
> 3. add property "qcom,phy-work-mode" for specifying qca8084 PHY
> work mode.
Why?
> 4. add the initial clocks and resets.
Why only initial, not final?
>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
> .../devicetree/bindings/net/qca,ar803x.yaml | 158 +++++++++++++++++-
> 1 file changed, 155 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> index 3acd09f0da86..febff039a44f 100644
> --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
> @@ -14,9 +14,6 @@ maintainers:
> description: |
> Bindings for Qualcomm Atheros AR803x PHYs
>
> -allOf:
> - - $ref: ethernet-phy.yaml#
> -
> properties:
> qca,clk-out-frequency:
> description: Clock output frequency in Hertz.
> @@ -85,6 +82,161 @@ properties:
> $ref: /schemas/regulator/regulator.yaml
> unevaluatedProperties: false
>
> + qcom,phy-addr-fixup:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
Why no constraints?
> + description:
> + MDIO address for 4 PHY devices and 3 PCS devices
Why do you need to change MMIO address?
> +
> + qcom,phy-work-mode:
> + description: PHY device work mode.
Your description copies property name. Tell us something we don't
know... like the meaning of the vcalues.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1, 2, 3]
> +
> + clocks:
> + items:
> + - description: APB bridge clock
> + - description: AHB clock
> + - description: Security control clock
> + - description: TLMM clock
> + - description: TLMM AHB clock
> + - description: CNOC AHB clock
> + - description: MDIO AHB clock
> + - description: MDIO master AHB clock
> + - description: PCS0 system clock
> + - description: PCS1 system clock
> + - description: EPHY0 system clock
> + - description: EPHY1 system clock
> + - description: EPHY2 system clock
> + - description: EPHY3 system clock
> + description: PHY initial common clock configs
> +
> + clock-names:
> + items:
> + - const: apb_bridge
> + - const: ahb
> + - const: sec_ctrl_ahb
> + - const: tlmm
> + - const: tlmm_ahb
> + - const: cnoc_ahb
> + - const: mdio_ahb
> + - const: mdio_master_ahb
> + - const: srds0_sys
> + - const: srds1_sys
> + - const: gephy0_sys
> + - const: gephy1_sys
> + - const: gephy2_sys
> + - const: gephy3_sys
> +
> + resets:
> + items:
> + - description: PCS0 system reset
> + - description: PCS1 system reset
> + - description: EPHY0 system reset
> + - description: EPHY1 system reset
> + - description: EPHY2 system reset
> + - description: EPHY3 system reset
> + - description: EPHY0 software reset
> + - description: EPHY1 software reset
> + - description: EPHY2 software reset
> + - description: EPHY3 software reset
> + - description: Ethernet DSP reset
> + description: PHY initial common reset configs
> +
> + reset-names:
> + items:
> + - const: srds0_sys
> + - const: srds1_sys
> + - const: gephy0_sys
> + - const: gephy1_sys
> + - const: gephy2_sys
> + - const: gephy3_sys
> + - const: gephy0_soft
> + - const: gephy1_soft
> + - const: gephy2_soft
> + - const: gephy3_soft
> + - const: gephy_dsp
> +
> +allOf:
> + - $ref: ethernet-phy.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - ethernet-phy-id004d.d180
> + then:
> + properties:
> + clocks:
> + items:
> + - description: APB bridge clock
> + - description: AHB clock
> + - description: Security control clock
> + - description: TLMM clock
> + - description: TLMM AHB clock
> + - description: CNOC AHB clock
> + - description: MDIO AHB clock
> + - description: MDIO master AHB clock
> + - description: PCS0 system clock
> + - description: PCS1 system clock
> + - description: EPHY0 system clock
> + - description: EPHY1 system clock
> + - description: EPHY2 system clock
> + - description: EPHY3 system clock
> + clock-names:
> + items:
> + - const: apb_bridge
> + - const: ahb
> + - const: sec_ctrl_ahb
> + - const: tlmm
> + - const: tlmm_ahb
> + - const: cnoc_ahb
> + - const: mdio_ahb
> + - const: mdio_master_ahb
> + - const: srds0_sys
> + - const: srds1_sys
> + - const: gephy0_sys
> + - const: gephy1_sys
> + - const: gephy2_sys
> + - const: gephy3_sys
?!? Why do you duplicate properties?
> + resets:
> + items:
> + - description: PCS0 system reset
> + - description: PCS1 system reset
> + - description: EPHY0 system reset
> + - description: EPHY1 system reset
> + - description: EPHY2 system reset
> + - description: EPHY3 system reset
> + - description: EPHY0 software reset
> + - description: EPHY1 software reset
> + - description: EPHY2 software reset
> + - description: EPHY3 software reset
> + - description: Ethernet DSP reset
> + reset-names:
> + items:
> + - const: srds0_sys
> + - const: srds1_sys
> + - const: gephy0_sys
> + - const: gephy1_sys
> + - const: gephy2_sys
> + - const: gephy3_sys
> + - const: gephy0_soft
> + - const: gephy1_soft
> + - const: gephy2_soft
> + - const: gephy3_soft
> + - const: gephy_dsp
> + required:
> + - qcom,phy-addr-fixup
> + - qcom,phy-work-mode
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + else:
> + properties:
> + qcom,phy-addr-fixup: false
> + qcom,phy-work-mode: false
And what about clcoks and resets for other variants? Your patch now
defined them for all variants without any explanation in commit msg.
> +
> unevaluatedProperties: false
>
> examples:
Best regards,
Krzysztof
@@ -14,9 +14,6 @@ maintainers:
description: |
Bindings for Qualcomm Atheros AR803x PHYs
-allOf:
- - $ref: ethernet-phy.yaml#
-
properties:
qca,clk-out-frequency:
description: Clock output frequency in Hertz.
@@ -85,6 +82,161 @@ properties:
$ref: /schemas/regulator/regulator.yaml
unevaluatedProperties: false
+ qcom,phy-addr-fixup:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ MDIO address for 4 PHY devices and 3 PCS devices
+
+ qcom,phy-work-mode:
+ description: PHY device work mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+
+ clocks:
+ items:
+ - description: APB bridge clock
+ - description: AHB clock
+ - description: Security control clock
+ - description: TLMM clock
+ - description: TLMM AHB clock
+ - description: CNOC AHB clock
+ - description: MDIO AHB clock
+ - description: MDIO master AHB clock
+ - description: PCS0 system clock
+ - description: PCS1 system clock
+ - description: EPHY0 system clock
+ - description: EPHY1 system clock
+ - description: EPHY2 system clock
+ - description: EPHY3 system clock
+ description: PHY initial common clock configs
+
+ clock-names:
+ items:
+ - const: apb_bridge
+ - const: ahb
+ - const: sec_ctrl_ahb
+ - const: tlmm
+ - const: tlmm_ahb
+ - const: cnoc_ahb
+ - const: mdio_ahb
+ - const: mdio_master_ahb
+ - const: srds0_sys
+ - const: srds1_sys
+ - const: gephy0_sys
+ - const: gephy1_sys
+ - const: gephy2_sys
+ - const: gephy3_sys
+
+ resets:
+ items:
+ - description: PCS0 system reset
+ - description: PCS1 system reset
+ - description: EPHY0 system reset
+ - description: EPHY1 system reset
+ - description: EPHY2 system reset
+ - description: EPHY3 system reset
+ - description: EPHY0 software reset
+ - description: EPHY1 software reset
+ - description: EPHY2 software reset
+ - description: EPHY3 software reset
+ - description: Ethernet DSP reset
+ description: PHY initial common reset configs
+
+ reset-names:
+ items:
+ - const: srds0_sys
+ - const: srds1_sys
+ - const: gephy0_sys
+ - const: gephy1_sys
+ - const: gephy2_sys
+ - const: gephy3_sys
+ - const: gephy0_soft
+ - const: gephy1_soft
+ - const: gephy2_soft
+ - const: gephy3_soft
+ - const: gephy_dsp
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id004d.d180
+ then:
+ properties:
+ clocks:
+ items:
+ - description: APB bridge clock
+ - description: AHB clock
+ - description: Security control clock
+ - description: TLMM clock
+ - description: TLMM AHB clock
+ - description: CNOC AHB clock
+ - description: MDIO AHB clock
+ - description: MDIO master AHB clock
+ - description: PCS0 system clock
+ - description: PCS1 system clock
+ - description: EPHY0 system clock
+ - description: EPHY1 system clock
+ - description: EPHY2 system clock
+ - description: EPHY3 system clock
+ clock-names:
+ items:
+ - const: apb_bridge
+ - const: ahb
+ - const: sec_ctrl_ahb
+ - const: tlmm
+ - const: tlmm_ahb
+ - const: cnoc_ahb
+ - const: mdio_ahb
+ - const: mdio_master_ahb
+ - const: srds0_sys
+ - const: srds1_sys
+ - const: gephy0_sys
+ - const: gephy1_sys
+ - const: gephy2_sys
+ - const: gephy3_sys
+ resets:
+ items:
+ - description: PCS0 system reset
+ - description: PCS1 system reset
+ - description: EPHY0 system reset
+ - description: EPHY1 system reset
+ - description: EPHY2 system reset
+ - description: EPHY3 system reset
+ - description: EPHY0 software reset
+ - description: EPHY1 software reset
+ - description: EPHY2 software reset
+ - description: EPHY3 software reset
+ - description: Ethernet DSP reset
+ reset-names:
+ items:
+ - const: srds0_sys
+ - const: srds1_sys
+ - const: gephy0_sys
+ - const: gephy1_sys
+ - const: gephy2_sys
+ - const: gephy3_sys
+ - const: gephy0_soft
+ - const: gephy1_soft
+ - const: gephy2_soft
+ - const: gephy3_soft
+ - const: gephy_dsp
+ required:
+ - qcom,phy-addr-fixup
+ - qcom,phy-work-mode
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ else:
+ properties:
+ qcom,phy-addr-fixup: false
+ qcom,phy-work-mode: false
+
unevaluatedProperties: false
examples: