Message ID | 20221120082114.3030-6-jszhang@kernel.org |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 21-20020a630215000000b00476e62744a8si8345508pgc.388.2022.11.20.00.32.34; Sun, 20 Nov 2022 00:32:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=BK1xeblc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229678AbiKTIbw (ORCPT <rfc822;aposhian.dev@gmail.com> + 99 others); Sun, 20 Nov 2022 03:31:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229622AbiKTIbW (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Sun, 20 Nov 2022 03:31:22 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D08619B7F2; Sun, 20 Nov 2022 00:31:19 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6B22A60BD8; Sun, 20 Nov 2022 08:31:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70061C433D7; Sun, 20 Nov 2022 08:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668933078; bh=G24oZBjdPa3JbPx8QD0rcb78CE3hAe3N+R48CzLmQsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BK1xeblcBO6cUVnXQGeMig9JelFSOfuq0mmQFNU8NlS5d7hQMwViz23z2YdP89A26 mx2UhCcMAyA95O5Jmej/MnOzO7JwyYflRQs2bjvopMFZzxIDRNBcKinjyXkRKwX128 ZE7J4Z48p0i+OgXiKQoy84j+u8PN14kQldumMNpOIXVkxh8aOeiJ0r4oyEVmag+FMz 0eCLkBkYwziWGBXLBzRF2BkTHhyQrDG/lzSIh2q3XUxFj5P3mGl85n5Vs2QOieX7pO YcLJqpmJAs3bvsYXdT3lLvLYFXU/3vL3wyhulv3EjV4WFT9VNUODHStDum2bUetyfd 1hJmvkCM/x1bg== From: Jisheng Zhang <jszhang@kernel.org> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jiri Slaby <jirislaby@kernel.org> Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Date: Sun, 20 Nov 2022 16:21:12 +0800 Message-Id: <20221120082114.3030-6-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221120082114.3030-1-jszhang@kernel.org> References: <20221120082114.3030-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750003265378313410?= X-GMAIL-MSGID: =?utf-8?q?1750003265378313410?= |
Series |
riscv: add Bouffalolab bl808 support
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Commit Message
Jisheng Zhang
Nov. 20, 2022, 8:21 a.m. UTC
Add a baisc dtsi for the bouffalolab bl808 SoC.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
Comments
On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..c98ebb14ee10 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; So this is not yet defined as the dt etc for the d1 has not yet landed. I think I will go pick up that patch for v6.2 as it should make everyone's life easier. Without that, dtbs_check produces: arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: /cpus/cpu@0: failed to match any schema with compatible: ['thead,c906', 'riscv'] > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; > + clock-output-names = "xtal"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; Hmm, this one fails validation too. Likely you need to add a "bouffalolab,plic" to the plic dt-binding or otherwise modify the binding such that thead,c900-plic on it's own is permitted. CC Samuel on that patch please in case he has an opinion on it. Also, I've taken over picking up the misc dt stuff that Palmer used to apply - so canaan, starfive & sifive stuff. Do you intended sending PRs to Arnd for this stuff, or would you like to me bundle it with what I am going to be sending anyway? Thanks, Conor. > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; > + }; > + }; > +}; > -- > 2.37.2 >
在 2022-11-20星期日的 11:02 +0000,Conor Dooley写道: > On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 2 files changed, 75 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile > > b/arch/riscv/boot/dts/Makefile > > index ff174996cdfd..b525467152b2 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += bouffalolab > > subdir-y += sifive > > subdir-y += starfive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..c98ebb14ee10 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > So this is not yet defined as the dt etc for the d1 has not yet > landed. > I think I will go pick up that patch for v6.2 as it should make > everyone's life easier. > > Without that, dtbs_check produces: > arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: > /cpus/cpu@0: failed to match any schema with compatible: > ['thead,c906', 'riscv'] > > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > + compatible = "bouffalolab,uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; > > Hmm, this one fails validation too. Likely you need to add a > "bouffalolab,plic" to the plic dt-binding or otherwise modify the > binding such that thead,c900-plic on it's own is permitted. CC Samuel > on > that patch please in case he has an opinion on it. Personally I prefer a single c900-plic in compatible, because the PLIC doesn't look so configurable in C906/C910 (the interrupt source number is really adjustable, but it's already in the riscv,ndev property). > > Also, I've taken over picking up the misc dt stuff that Palmer used > to > apply - so canaan, starfive & sifive stuff. Do you intended sending > PRs > to Arnd for this stuff, or would you like to me bundle it with what I > am > going to be sending anyway? > > Thanks, > Conor. > > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > + }; > > + }; > > +}; > > -- > > 2.37.2 > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Sun, Nov 20, 2022 at 07:58:56PM +0800, Icenowy Zheng wrote: > 在 2022-11-20星期日的 11:02 +0000,Conor Dooley写道: > > On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > > Hmm, this one fails validation too. Likely you need to add a > > "bouffalolab,plic" to the plic dt-binding or otherwise modify the > > binding such that thead,c900-plic on it's own is permitted. CC Samuel > > on > > that patch please in case he has an opinion on it. > > Personally I prefer a single c900-plic in compatible, because the PLIC > doesn't look so configurable in C906/C910 (the interrupt source number > is really adjustable, but it's already in the riscv,ndev property). Right, if all implementations are going to be identical (modulo the riscv,ndev) allowing thead,c900-plic in isolation makes sense to me. I had a bit of a check in the history & it looks like there was no explanation given for why the D1 needed a specific compatible (although there's no harm in having one in case something comes up in the future that'd require special handling for a given implementation).
On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..c98ebb14ee10 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; This was discussed many times before, but I think the conclusion was that the frequency is a property of the crystal on the board, so this should be 0 in the SoC dtsi, and then overwritten in the board device tree. > + clock-output-names = "xtal"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; > + }; > + }; > +}; > -- > 2.37.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote: > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > This was discussed many times before, but I think the conclusion was > that the frequency is a property of the crystal on the board, so this > should be 0 in the SoC dtsi, and then overwritten in the board device > tree. Or set nothing in soc.dtsi so that dtbs_check can be used to see if someone forgot to set a clock for their board? > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + };
On Sun, 20 Nov 2022 at 18:51, Conor Dooley <conor@kernel.org> wrote: > > On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote: > > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > + xtal: xtal-clk { > > > + compatible = "fixed-clock"; > > > + clock-frequency = <40000000>; > > > > This was discussed many times before, but I think the conclusion was > > that the frequency is a property of the crystal on the board, so this > > should be 0 in the SoC dtsi, and then overwritten in the board device > > tree. > > Or set nothing in soc.dtsi so that dtbs_check can be used to see if > someone forgot to set a clock for their board? Sure. That sounds even better. > > > + clock-output-names = "xtal"; > > > + #clock-cells = <0>; > > > + }; >
在 2022-11-20星期日的 15:57 +0100,Emil Renner Berthing写道: > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> > wrote: > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 2 files changed, 75 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile > > b/arch/riscv/boot/dts/Makefile > > index ff174996cdfd..b525467152b2 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += bouffalolab > > subdir-y += sifive > > subdir-y += starfive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..c98ebb14ee10 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > This was discussed many times before, but I think the conclusion was > that the frequency is a property of the crystal on the board, so this > should be 0 in the SoC dtsi, and then overwritten in the board device > tree. But many chips just specify an accepted frequency in their datasheet, and using a frequency other than this is undefined behavior. > > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > + compatible = "bouffalolab,uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > + }; > > + }; > > +}; > > -- > > 2.37.2 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 20/11/2022 09:21, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab Nothing to build there, so not yet. Best regards, Krzysztof
On Mon, 21 Nov 2022 at 04:37, Icenowy Zheng <uwu@icenowy.me> wrote: > > 在 2022-11-20星期日的 15:57 +0100,Emil Renner Berthing写道: > > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> > > wrote: > > > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > ++++++++++++++++++++++ > > > 2 files changed, 75 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/Makefile > > > b/arch/riscv/boot/dts/Makefile > > > index ff174996cdfd..b525467152b2 100644 > > > --- a/arch/riscv/boot/dts/Makefile > > > +++ b/arch/riscv/boot/dts/Makefile > > > @@ -1,4 +1,5 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > +subdir-y += bouffalolab > > > subdir-y += sifive > > > subdir-y += starfive > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > new file mode 100644 > > > index 000000000000..c98ebb14ee10 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > @@ -0,0 +1,74 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > > +/* > > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > > + */ > > > + > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > + > > > +/ { > > > + compatible = "bouffalolab,bl808"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + cpus { > > > + timebase-frequency = <1000000>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + compatible = "thead,c906", "riscv"; > > > + device_type = "cpu"; > > > + reg = <0>; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <256>; > > > + d-cache-size = <32768>; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <128>; > > > + i-cache-size = <32768>; > > > + mmu-type = "riscv,sv39"; > > > + riscv,isa = "rv64imafdc"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + xtal: xtal-clk { > > > + compatible = "fixed-clock"; > > > + clock-frequency = <40000000>; > > > > This was discussed many times before, but I think the conclusion was > > that the frequency is a property of the crystal on the board, so this > > should be 0 in the SoC dtsi, and then overwritten in the board device > > tree. > > But many chips just specify an accepted frequency in their datasheet, > and using a frequency other than this is undefined behavior. Yes, this was the argument in previous discussions, but the conclusion was still that it should go in the board dts. To be clear I'm just summing up the conclusion from previous discussions about this, and have no strong opinion other than we should do the same everywhere. > > > > > + clock-output-names = "xtal"; > > > + #clock-cells = <0>; > > > + }; > > > + > > > + soc { > > > + compatible = "simple-bus"; > > > + ranges; > > > + interrupt-parent = <&plic>; > > > + dma-noncoherent; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + uart0: serial@30002000 { > > > + compatible = "bouffalolab,uart"; > > > + reg = <0x30002000 0x1000>; > > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&xtal>; > > > + status = "disabled"; > > > + }; > > > + > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > + }; > > > + }; > > > +}; > > > -- > > > 2.37.2 > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b525467152b2 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += bouffalolab subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 000000000000..c98ebb14ee10 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <64>; + }; + }; +};