diff mbox series

[5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree

Message ID 20221120082114.3030-6-jszhang@kernel.org
State New
Headers
Series riscv: add Bouffalolab bl808 support |

Commit Message

Jisheng Zhang Nov. 20, 2022, 8:21 a.m. UTC 
  Add a baisc dtsi for the bouffalolab bl808 SoC.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/Makefile               |  1 +
 arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi

Comments

Conor Dooley Nov. 20, 2022, 11:02 a.m. UTC | #1 
On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote:
> Add a baisc dtsi for the bouffalolab bl808 SoC.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/Makefile               |  1 +
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
>  2 files changed, 75 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 000000000000..c98ebb14ee10
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "bouffalolab,bl808";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		timebase-frequency = <1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "thead,c906", "riscv";

So this is not yet defined as the dt etc for the d1 has not yet landed.
I think I will go pick up that patch for v6.2 as it should make
everyone's life easier.

Without that, dtbs_check produces:
arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: /cpus/cpu@0: failed to match any schema with compatible: ['thead,c906', 'riscv']

> +			device_type = "cpu";
> +			reg = <0>;
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <256>;
> +			d-cache-size = <32768>;
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			mmu-type = "riscv,sv39";
> +			riscv,isa = "rv64imafdc";
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	xtal: xtal-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <40000000>;
> +		clock-output-names = "xtal";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&plic>;
> +		dma-noncoherent;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		uart0: serial@30002000 {
> +			compatible = "bouffalolab,uart";
> +			reg = <0x30002000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&xtal>;
> +			status = "disabled";
> +		};
> +
> +		plic: interrupt-controller@e0000000 {
> +			compatible = "thead,c900-plic";

Hmm, this one fails validation too. Likely you need to add a
"bouffalolab,plic" to the plic dt-binding or otherwise modify the
binding such that thead,c900-plic on it's own is permitted. CC Samuel on
that patch please in case he has an opinion on it.

Also, I've taken over picking up the misc dt stuff that Palmer used to
apply - so canaan, starfive & sifive stuff. Do you intended sending PRs
to Arnd for this stuff, or would you like to me bundle it with what I am
going to be sending anyway?

Thanks,
Conor.

> +			reg = <0xe0000000 0x4000000>;
> +			interrupts-extended = <&cpu0_intc 0xffffffff>,
> +					      <&cpu0_intc 9>;
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			riscv,ndev = <64>;
> +		};
> +	};
> +};
> -- 
> 2.37.2
>
Icenowy Zheng Nov. 20, 2022, 11:58 a.m. UTC | #2 
在 2022-11-20星期日的 11:02 +0000，Conor Dooley写道：
> On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote:
> > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/Makefile               |  1 +
> >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > ++++++++++++++++++++++
> >  2 files changed, 75 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b525467152b2 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,4 +1,5 @@
> >  # SPDX-License-Identifier: GPL-2.0
> > +subdir-y += bouffalolab
> >  subdir-y += sifive
> >  subdir-y += starfive
> >  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > new file mode 100644
> > index 000000000000..c98ebb14ee10
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "bouffalolab,bl808";
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               timebase-frequency = <1000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> 
> So this is not yet defined as the dt etc for the d1 has not yet
> landed.
> I think I will go pick up that patch for v6.2 as it should make
> everyone's life easier.
> 
> Without that, dtbs_check produces:
> arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0:
> /cpus/cpu@0: failed to match any schema with compatible:
> ['thead,c906', 'riscv']
> 
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       riscv,isa = "rv64imafdc";
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <40000000>;
> > +               clock-output-names = "xtal";
> > +               #clock-cells = <0>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               interrupt-parent = <&plic>;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               uart0: serial@30002000 {
> > +                       compatible = "bouffalolab,uart";
> > +                       reg = <0x30002000 0x1000>;
> > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&xtal>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               plic: interrupt-controller@e0000000 {
> > +                       compatible = "thead,c900-plic";
> 
> Hmm, this one fails validation too. Likely you need to add a
> "bouffalolab,plic" to the plic dt-binding or otherwise modify the
> binding such that thead,c900-plic on it's own is permitted. CC Samuel
> on
> that patch please in case he has an opinion on it.

Personally I prefer a single c900-plic in compatible, because the PLIC
doesn't look so configurable in C906/C910 (the interrupt source number
is really adjustable, but it's already in the riscv,ndev property).

> 
> Also, I've taken over picking up the misc dt stuff that Palmer used
> to
> apply - so canaan, starfive & sifive stuff. Do you intended sending
> PRs
> to Arnd for this stuff, or would you like to me bundle it with what I
> am
> going to be sending anyway?
> 
> Thanks,
> Conor.
> 
> > +                       reg = <0xe0000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc
> > 0xffffffff>,
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +                       riscv,ndev = <64>;
> > +               };
> > +       };
> > +};
> > -- 
> > 2.37.2
> > 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Conor Dooley Nov. 20, 2022, 2:28 p.m. UTC | #3 
On Sun, Nov 20, 2022 at 07:58:56PM +0800, Icenowy Zheng wrote:
> 在 2022-11-20星期日的 11:02 +0000，Conor Dooley写道：
> > On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote:
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.

> > > +               plic: interrupt-controller@e0000000 {
> > > +                       compatible = "thead,c900-plic";
> > 
> > Hmm, this one fails validation too. Likely you need to add a
> > "bouffalolab,plic" to the plic dt-binding or otherwise modify the
> > binding such that thead,c900-plic on it's own is permitted. CC Samuel
> > on
> > that patch please in case he has an opinion on it.
> 
> Personally I prefer a single c900-plic in compatible, because the PLIC
> doesn't look so configurable in C906/C910 (the interrupt source number
> is really adjustable, but it's already in the riscv,ndev property).

Right, if all implementations are going to be identical (modulo the
riscv,ndev) allowing thead,c900-plic in isolation makes sense to me.
I had a bit of a check in the history & it looks like there was no 
explanation given for why the D1 needed a specific compatible (although
there's no harm in having one in case something comes up in the future
that'd require special handling for a given implementation).
Emil Renner Berthing Nov. 20, 2022, 2:57 p.m. UTC | #4 
On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote:
>
> Add a baisc dtsi for the bouffalolab bl808 SoC.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/Makefile               |  1 +
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
>  2 files changed, 75 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab
>  subdir-y += sifive
>  subdir-y += starfive
>  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> new file mode 100644
> index 000000000000..c98ebb14ee10
> --- /dev/null
> +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +       compatible = "bouffalolab,bl808";
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       cpus {
> +               timebase-frequency = <1000000>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu0: cpu@0 {
> +                       compatible = "thead,c906", "riscv";
> +                       device_type = "cpu";
> +                       reg = <0>;
> +                       d-cache-block-size = <64>;
> +                       d-cache-sets = <256>;
> +                       d-cache-size = <32768>;
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <128>;
> +                       i-cache-size = <32768>;
> +                       mmu-type = "riscv,sv39";
> +                       riscv,isa = "rv64imafdc";
> +
> +                       cpu0_intc: interrupt-controller {
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                               #address-cells = <0>;
> +                               #interrupt-cells = <1>;
> +                       };
> +               };
> +       };
> +
> +       xtal: xtal-clk {
> +               compatible = "fixed-clock";
> +               clock-frequency = <40000000>;

This was discussed many times before, but I think the conclusion was
that the frequency is a property of the crystal on the board, so this
should be 0 in the SoC dtsi, and then overwritten in the board device
tree.

> +               clock-output-names = "xtal";
> +               #clock-cells = <0>;
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               ranges;
> +               interrupt-parent = <&plic>;
> +               dma-noncoherent;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +
> +               uart0: serial@30002000 {
> +                       compatible = "bouffalolab,uart";
> +                       reg = <0x30002000 0x1000>;
> +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&xtal>;
> +                       status = "disabled";
> +               };
> +
> +               plic: interrupt-controller@e0000000 {
> +                       compatible = "thead,c900-plic";
> +                       reg = <0xe0000000 0x4000000>;
> +                       interrupts-extended = <&cpu0_intc 0xffffffff>,
> +                                             <&cpu0_intc 9>;
> +                       interrupt-controller;
> +                       #address-cells = <0>;
> +                       #interrupt-cells = <2>;
> +                       riscv,ndev = <64>;
> +               };
> +       };
> +};
> --
> 2.37.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Conor Dooley Nov. 20, 2022, 5:51 p.m. UTC | #5 
On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote:
> On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Add a baisc dtsi for the bouffalolab bl808 SoC.

> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <40000000>;
> 
> This was discussed many times before, but I think the conclusion was
> that the frequency is a property of the crystal on the board, so this
> should be 0 in the SoC dtsi, and then overwritten in the board device
> tree.

Or set nothing in soc.dtsi so that dtbs_check can be used to see if
someone forgot to set a clock for their board?

> > +               clock-output-names = "xtal";
> > +               #clock-cells = <0>;
> > +       };
Emil Renner Berthing Nov. 20, 2022, 6:33 p.m. UTC | #6 
On Sun, 20 Nov 2022 at 18:51, Conor Dooley <conor@kernel.org> wrote:
>
> On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote:
> > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote:
> > >
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.
>
> > > +       xtal: xtal-clk {
> > > +               compatible = "fixed-clock";
> > > +               clock-frequency = <40000000>;
> >
> > This was discussed many times before, but I think the conclusion was
> > that the frequency is a property of the crystal on the board, so this
> > should be 0 in the SoC dtsi, and then overwritten in the board device
> > tree.
>
> Or set nothing in soc.dtsi so that dtbs_check can be used to see if
> someone forgot to set a clock for their board?

Sure. That sounds even better.

> > > +               clock-output-names = "xtal";
> > > +               #clock-cells = <0>;
> > > +       };
>
Icenowy Zheng Nov. 21, 2022, 3:36 a.m. UTC | #7 
在 2022-11-20星期日的 15:57 +0100，Emil Renner Berthing写道：
> On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org>
> wrote:
> > 
> > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/Makefile               |  1 +
> >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > ++++++++++++++++++++++
> >  2 files changed, 75 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b525467152b2 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,4 +1,5 @@
> >  # SPDX-License-Identifier: GPL-2.0
> > +subdir-y += bouffalolab
> >  subdir-y += sifive
> >  subdir-y += starfive
> >  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > new file mode 100644
> > index 000000000000..c98ebb14ee10
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "bouffalolab,bl808";
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               timebase-frequency = <1000000>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "thead,c906", "riscv";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       d-cache-block-size = <64>;
> > +                       d-cache-sets = <256>;
> > +                       d-cache-size = <32768>;
> > +                       i-cache-block-size = <64>;
> > +                       i-cache-sets = <128>;
> > +                       i-cache-size = <32768>;
> > +                       mmu-type = "riscv,sv39";
> > +                       riscv,isa = "rv64imafdc";
> > +
> > +                       cpu0_intc: interrupt-controller {
> > +                               compatible = "riscv,cpu-intc";
> > +                               interrupt-controller;
> > +                               #address-cells = <0>;
> > +                               #interrupt-cells = <1>;
> > +                       };
> > +               };
> > +       };
> > +
> > +       xtal: xtal-clk {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <40000000>;
> 
> This was discussed many times before, but I think the conclusion was
> that the frequency is a property of the crystal on the board, so this
> should be 0 in the SoC dtsi, and then overwritten in the board device
> tree.

But many chips just specify an accepted frequency in their datasheet,
and using a frequency other than this is undefined behavior.

> 
> > +               clock-output-names = "xtal";
> > +               #clock-cells = <0>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               ranges;
> > +               interrupt-parent = <&plic>;
> > +               dma-noncoherent;
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +
> > +               uart0: serial@30002000 {
> > +                       compatible = "bouffalolab,uart";
> > +                       reg = <0x30002000 0x1000>;
> > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&xtal>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               plic: interrupt-controller@e0000000 {
> > +                       compatible = "thead,c900-plic";
> > +                       reg = <0xe0000000 0x4000000>;
> > +                       interrupts-extended = <&cpu0_intc
> > 0xffffffff>,
> > +                                             <&cpu0_intc 9>;
> > +                       interrupt-controller;
> > +                       #address-cells = <0>;
> > +                       #interrupt-cells = <2>;
> > +                       riscv,ndev = <64>;
> > +               };
> > +       };
> > +};
> > --
> > 2.37.2
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Krzysztof Kozlowski Nov. 21, 2022, 10:09 a.m. UTC | #8 
On 20/11/2022 09:21, Jisheng Zhang wrote:
> Add a baisc dtsi for the bouffalolab bl808 SoC.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/Makefile               |  1 +
>  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++
>  2 files changed, 75 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b525467152b2 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += bouffalolab

Nothing to build there, so not yet.


Best regards,
Krzysztof
Emil Renner Berthing Nov. 21, 2022, 11:25 a.m. UTC | #9 
On Mon, 21 Nov 2022 at 04:37, Icenowy Zheng <uwu@icenowy.me> wrote:
>
> 在 2022-11-20星期日的 15:57 +0100，Emil Renner Berthing写道：
> > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org>
> > wrote:
> > >
> > > Add a baisc dtsi for the bouffalolab bl808 SoC.
> > >
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/boot/dts/Makefile               |  1 +
> > >  arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74
> > > ++++++++++++++++++++++
> > >  2 files changed, 75 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/Makefile
> > > b/arch/riscv/boot/dts/Makefile
> > > index ff174996cdfd..b525467152b2 100644
> > > --- a/arch/riscv/boot/dts/Makefile
> > > +++ b/arch/riscv/boot/dts/Makefile
> > > @@ -1,4 +1,5 @@
> > >  # SPDX-License-Identifier: GPL-2.0
> > > +subdir-y += bouffalolab
> > >  subdir-y += sifive
> > >  subdir-y += starfive
> > >  subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > new file mode 100644
> > > index 000000000000..c98ebb14ee10
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
> > > @@ -0,0 +1,74 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +/*
> > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
> > > + */
> > > +
> > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > +
> > > +/ {
> > > +       compatible = "bouffalolab,bl808";
> > > +       #address-cells = <1>;
> > > +       #size-cells = <1>;
> > > +
> > > +       cpus {
> > > +               timebase-frequency = <1000000>;
> > > +               #address-cells = <1>;
> > > +               #size-cells = <0>;
> > > +
> > > +               cpu0: cpu@0 {
> > > +                       compatible = "thead,c906", "riscv";
> > > +                       device_type = "cpu";
> > > +                       reg = <0>;
> > > +                       d-cache-block-size = <64>;
> > > +                       d-cache-sets = <256>;
> > > +                       d-cache-size = <32768>;
> > > +                       i-cache-block-size = <64>;
> > > +                       i-cache-sets = <128>;
> > > +                       i-cache-size = <32768>;
> > > +                       mmu-type = "riscv,sv39";
> > > +                       riscv,isa = "rv64imafdc";
> > > +
> > > +                       cpu0_intc: interrupt-controller {
> > > +                               compatible = "riscv,cpu-intc";
> > > +                               interrupt-controller;
> > > +                               #address-cells = <0>;
> > > +                               #interrupt-cells = <1>;
> > > +                       };
> > > +               };
> > > +       };
> > > +
> > > +       xtal: xtal-clk {
> > > +               compatible = "fixed-clock";
> > > +               clock-frequency = <40000000>;
> >
> > This was discussed many times before, but I think the conclusion was
> > that the frequency is a property of the crystal on the board, so this
> > should be 0 in the SoC dtsi, and then overwritten in the board device
> > tree.
>
> But many chips just specify an accepted frequency in their datasheet,
> and using a frequency other than this is undefined behavior.

Yes, this was the argument in previous discussions, but the conclusion
was still that it should go in the board dts. To be clear I'm just
summing up the conclusion from previous discussions about this, and
have no strong opinion other than we should do the same everywhere.

> >
> > > +               clock-output-names = "xtal";
> > > +               #clock-cells = <0>;
> > > +       };
> > > +
> > > +       soc {
> > > +               compatible = "simple-bus";
> > > +               ranges;
> > > +               interrupt-parent = <&plic>;
> > > +               dma-noncoherent;
> > > +               #address-cells = <1>;
> > > +               #size-cells = <1>;
> > > +
> > > +               uart0: serial@30002000 {
> > > +                       compatible = "bouffalolab,uart";
> > > +                       reg = <0x30002000 0x1000>;
> > > +                       interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&xtal>;
> > > +                       status = "disabled";
> > > +               };
> > > +
> > > +               plic: interrupt-controller@e0000000 {
> > > +                       compatible = "thead,c900-plic";
> > > +                       reg = <0xe0000000 0x4000000>;
> > > +                       interrupts-extended = <&cpu0_intc
> > > 0xffffffff>,
> > > +                                             <&cpu0_intc 9>;
> > > +                       interrupt-controller;
> > > +                       #address-cells = <0>;
> > > +                       #interrupt-cells = <2>;
> > > +                       riscv,ndev = <64>;
> > > +               };
> > > +       };
> > > +};
> > > --
> > > 2.37.2
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b525467152b2 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,4 +1,5 @@ 
 # SPDX-License-Identifier: GPL-2.0
+subdir-y += bouffalolab
 subdir-y += sifive
 subdir-y += starfive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
new file mode 100644
index 000000000000..c98ebb14ee10
--- /dev/null
+++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi
@@ -0,0 +1,74 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "bouffalolab,bl808";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		timebase-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "thead,c906", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			mmu-type = "riscv,sv39";
+			riscv,isa = "rv64imafdc";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&plic>;
+		dma-noncoherent;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@30002000 {
+			compatible = "bouffalolab,uart";
+			reg = <0x30002000 0x1000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtal>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "thead,c900-plic";
+			reg = <0xe0000000 0x4000000>;
+			interrupts-extended = <&cpu0_intc 0xffffffff>,
+					      <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <64>;
+		};
+	};
+};