clk: microchip: check for null return of devm_kzalloc()

Message ID 20221119054858.178629-1-tanghui20@huawei.com
State New
Headers
Series clk: microchip: check for null return of devm_kzalloc() |

Commit Message

Hui Tang Nov. 19, 2022, 5:48 a.m. UTC
  Because of the possilble failure of devm_kzalloc(), name might be NULL and
will cause null pointer derefrence later.

Therefore, it might be better to check it and directly return -ENOMEM.

Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support")
Signed-off-by: Hui Tang <tanghui20@huawei.com>
---
 drivers/clk/microchip/clk-mpfs-ccc.c | 6 ++++++
 1 file changed, 6 insertions(+)
  

Comments

Conor Dooley Nov. 19, 2022, 10:43 a.m. UTC | #1
On Sat, Nov 19, 2022 at 01:48:58PM +0800, Hui Tang wrote:
> Because of the possilble failure of devm_kzalloc(), name might be NULL and
> will cause null pointer derefrence later.

In theory, yeah?

(note to self, s/refrence/reference/, s/possilble/possible)

> Therefore, it might be better to check it and directly return -ENOMEM.

I agree with your use of might here. If the allocations do fail, we
likely aren't getting the system off the ground anyway - but there is
no harm in checking.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

@Claudiu, supposedly I can push to the at91 repo now so I will try to do
that.

Thanks,
Conor.

> 
> Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support")
> Signed-off-by: Hui Tang <tanghui20@huawei.com>
> ---
>  drivers/clk/microchip/clk-mpfs-ccc.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c
> index 7be028dced63..32aae880a14f 100644
> --- a/drivers/clk/microchip/clk-mpfs-ccc.c
> +++ b/drivers/clk/microchip/clk-mpfs-ccc.c
> @@ -166,6 +166,9 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
>  		struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
>  		char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
>  
> +		if (!name)
> +			return -ENOMEM;
> +
>  		snprintf(name, 23, "%s_out%u", parent->name, i);
>  		out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
>  		out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
> @@ -200,6 +203,9 @@ static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
>  		struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
>  		char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
>  
> +		if (!name)
> +			return -ENOMEM;
> +
>  		pll_hw->base = data->pll_base[i];
>  		snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
>  		pll_hw->name = (const char *)name;
> -- 
> 2.17.1
>
  
Hui Tang Nov. 21, 2022, 7:26 a.m. UTC | #2
On 2022/11/19 18:43, Conor Dooley wrote:
> On Sat, Nov 19, 2022 at 01:48:58PM +0800, Hui Tang wrote:
>> Because of the possilble failure of devm_kzalloc(), name might be NULL and
>> will cause null pointer derefrence later.
>
> In theory, yeah?
>
> (note to self, s/refrence/reference/, s/possilble/possible)

Sorry, I make spelling mistakes.

Thanks.
  
Claudiu Beznea Nov. 25, 2022, 1:48 p.m. UTC | #3
On 19.11.2022 12:43, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Sat, Nov 19, 2022 at 01:48:58PM +0800, Hui Tang wrote:
>> Because of the possilble failure of devm_kzalloc(), name might be NULL and
>> will cause null pointer derefrence later.
> 
> In theory, yeah?
> 
> (note to self, s/refrence/reference/, s/possilble/possible)

Applied to clk-microchip-fixes with these adjustments, thanks!

> 
>> Therefore, it might be better to check it and directly return -ENOMEM.
> 
> I agree with your use of might here. If the allocations do fail, we
> likely aren't getting the system off the ground anyway - but there is
> no harm in checking.
> 
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> @Claudiu, supposedly I can push to the at91 repo now so I will try to do
> that.
> 
> Thanks,
> Conor.
> 
>>
>> Fixes: d39fb172760e ("clk: microchip: add PolarFire SoC fabric clock support")
>> Signed-off-by: Hui Tang <tanghui20@huawei.com>
>> ---
>>  drivers/clk/microchip/clk-mpfs-ccc.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c
>> index 7be028dced63..32aae880a14f 100644
>> --- a/drivers/clk/microchip/clk-mpfs-ccc.c
>> +++ b/drivers/clk/microchip/clk-mpfs-ccc.c
>> @@ -166,6 +166,9 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
>>               struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
>>               char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
>>
>> +             if (!name)
>> +                     return -ENOMEM;
>> +
>>               snprintf(name, 23, "%s_out%u", parent->name, i);
>>               out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
>>               out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
>> @@ -200,6 +203,9 @@ static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
>>               struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
>>               char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
>>
>> +             if (!name)
>> +                     return -ENOMEM;
>> +
>>               pll_hw->base = data->pll_base[i];
>>               snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
>>               pll_hw->name = (const char *)name;
>> --
>> 2.17.1
>>
  

Patch

diff --git a/drivers/clk/microchip/clk-mpfs-ccc.c b/drivers/clk/microchip/clk-mpfs-ccc.c
index 7be028dced63..32aae880a14f 100644
--- a/drivers/clk/microchip/clk-mpfs-ccc.c
+++ b/drivers/clk/microchip/clk-mpfs-ccc.c
@@ -166,6 +166,9 @@  static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
 		struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
 		char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
 
+		if (!name)
+			return -ENOMEM;
+
 		snprintf(name, 23, "%s_out%u", parent->name, i);
 		out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
 		out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
@@ -200,6 +203,9 @@  static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
 		struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
 		char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
 
+		if (!name)
+			return -ENOMEM;
+
 		pll_hw->base = data->pll_base[i];
 		snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
 		pll_hw->name = (const char *)name;