[v2,14/14] clk: starfive: jh71x0: Don't register aux devices if JH7110 reset is disabled
Message ID | 20221118010627.70576-15-hal.feng@starfivetech.com |
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State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d17-20020a17090ad99100b0020af2411705si2073462pjv.104.2022.11.17.17.48.27; Thu, 17 Nov 2022 17:48:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240956AbiKRBoP convert rfc822-to-8bit (ORCPT <rfc822;a1648639935@gmail.com> + 99 others); Thu, 17 Nov 2022 20:44:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240912AbiKRBoN (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 17 Nov 2022 20:44:13 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D891473B98; Thu, 17 Nov 2022 17:44:12 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 8B7A824E047; Fri, 18 Nov 2022 09:06:39 +0800 (CST) Received: from EXMBX072.cuchost.com (172.16.6.82) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:06:39 +0800 Received: from ubuntu.localdomain (183.27.96.116) by EXMBX072.cuchost.com (172.16.6.82) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 18 Nov 2022 09:06:38 +0800 From: Hal Feng <hal.feng@starfivetech.com> To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org> CC: Conor Dooley <conor@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Stephen Boyd <sboyd@kernel.org>, "Michael Turquette" <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Hal Feng <hal.feng@starfivetech.com>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 14/14] clk: starfive: jh71x0: Don't register aux devices if JH7110 reset is disabled Date: Fri, 18 Nov 2022 09:06:27 +0800 Message-ID: <20221118010627.70576-15-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118010627.70576-1-hal.feng@starfivetech.com> References: <20221118010627.70576-1-hal.feng@starfivetech.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [183.27.96.116] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX072.cuchost.com (172.16.6.82) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749796647138381144?= X-GMAIL-MSGID: =?utf-8?q?1749796647138381144?= |
Series |
Basic clock and reset support for StarFive JH7110 RISC-V SoC
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Commit Message
Hal Feng
Nov. 18, 2022, 1:06 a.m. UTC
The JH7110 clock drivers will not register redundant auxiliary
devices if the JH7110 reset auxiliary driver is disabled.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
Comments
On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@starfivetech.com> wrote: > > The JH7110 clock drivers will not register redundant auxiliary > devices if the JH7110 reset auxiliary driver is disabled. > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > --- > drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c > index dda19c6937cb..4e69f56b00cc 100644 > --- a/drivers/clk/starfive/clk-starfive-jh71x0.c > +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c > @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) > } > EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); > > -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) > +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) I don't see any reason you'd want to build a kernel that needs the clock driver but not the resets, so I don't think this is something we should optimize for. I'd just drop this patch and let such broken kernels register the auxiliary devices even when no reset driver is there to use them. > static void jh7110_reset_unregister_adev(void *_adev) > { > @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, > } > EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); > > +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ > + > +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, > + const char *adev_name, > + u32 adev_id) > +{ > + return 0; > +} > + > #endif > -- > 2.38.1 >
On Sat, 19 Nov 2022 01:18:18 +0800, Emil Renner Berthing wrote: > On Fri, 18 Nov 2022 at 02:06, Hal Feng <hal.feng@starfivetech.com> wrote: >> >> The JH7110 clock drivers will not register redundant auxiliary >> devices if the JH7110 reset auxiliary driver is disabled. >> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> >> --- >> drivers/clk/starfive/clk-starfive-jh71x0.c | 11 ++++++++++- >> 1 file changed, 10 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c >> index dda19c6937cb..4e69f56b00cc 100644 >> --- a/drivers/clk/starfive/clk-starfive-jh71x0.c >> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c >> @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) >> } >> EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); >> >> -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) >> +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) > > I don't see any reason you'd want to build a kernel that needs the > clock driver but not the resets, so I don't think this is something we > should optimize for. I'd just drop this patch and let such broken > kernels register the auxiliary devices even when no reset driver is > there to use them. You're right. I made this patch just following the style of jh7100. And I think it's better to select RESET_STARFIVE_JH7110 in config CLK_STARFIVE_JH7110_SYS. Best regards, Hal > >> static void jh7110_reset_unregister_adev(void *_adev) >> { >> @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, >> } >> EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); >> >> +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ >> + >> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, >> + const char *adev_name, >> + u32 adev_id) >> +{ >> + return 0; >> +} >> + >> #endif
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c index dda19c6937cb..4e69f56b00cc 100644 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c @@ -333,7 +333,7 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) } EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); -#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS) +#if IS_ENABLED(CONFIG_RESET_STARFIVE_JH7110) static void jh7110_reset_unregister_adev(void *_adev) { @@ -384,4 +384,13 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, } EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); +#else /* !CONFIG_RESET_STARFIVE_JH7110 */ + +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, + const char *adev_name, + u32 adev_id) +{ + return 0; +} + #endif