diff mbox series

RISC-V: Support highest-number regno overlap for widen ternary vx instructions

Message ID 20231204101142.411128-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Support highest-number regno overlap for widen ternary vx instructions |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Dec. 4, 2023, 10:11 a.m. UTC 
  Consider this example:

#include "riscv_vector.h"
void
foo6 (void *in, void *out)
{
  vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4);
  vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1);
  vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64);
  vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i);
  vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i);
  vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32, 4);
  __riscv_vse64_v_f64m8 (out, result, 4);
}

Before this patch:

foo6:                                   # @foo6
        vsetivli        zero, 4, e32, m4, ta, ma
        vle64.v v8, (a0)
        lui     a0, 272384
        fmv.w.x fa5, a0
        vmv8r.v v16, v8
        vfwnmsac.vf     v16, fa5, v12
        vse64.v v16, (a1)
        ret

After this patch:

foo6:
.LFB5:
	.cfi_startproc
	lui	a5,%hi(.LC0)
	flw	fa5,%lo(.LC0)(a5)
	vsetivli	zero,4,e32,m4,ta,ma
	vle64.v	v8,0(a0)
	vfwnmsac.vf	v8,fa5,v12
	vse64.v	v8,0(a1)
	ret

	PR target/112431

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: New attributes.
	* config/riscv/vector.md: Support highest-number overlap for widen ternary vx.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-37.c: New test.
	* gcc.target/riscv/rvv/base/pr112431-38.c: New test.

---
 gcc/config/riscv/vector-iterators.md          | 1071 +++++++++++++++++
 gcc/config/riscv/vector.md                    |  115 +-
 .../gcc.target/riscv/rvv/base/pr112431-37.c   |  103 ++
 .../gcc.target/riscv/rvv/base/pr112431-38.c   |   82 ++
 4 files changed, 1316 insertions(+), 55 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c

Comments

Robin Dapp Dec. 4, 2023, 12:13 p.m. UTC | #1 
> +(define_mode_attr widen_ternop_dest_constraint [
> +  (RVVM8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM1QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM8HI "=vd, vr, vd, vr, vd, vr, ?&vr")
[...]

I'm fine with avoiding the overlap but I'm not sure this is
easily maintainable because the constraints don't actually
depend on the mode?  I suppose this is for easy re-use across
different insns but there are only six(?) widening patterns
so we don't even save lines of code by this?

I guess I would prefer the normal approach of writing it out
explicitly in the pattern.  Maybe add a different replacement
method like define_subst in the future to simplify such
situations?


+  "vwmacc<u>.vx\t%0,%z3,%4%p1"

Why the z here?  For canonicalization?

Regards
 Robin
juzhe.zhong@rivai.ai Dec. 4, 2023, 1:33 p.m. UTC | #2 
Adapt patch in V2 with explictly write constraints in the pattern:
[V2] RISC-V: Support highest-number regno overlap for widen ternary - Patchwork (sourceware.org)

Thanks.



juzhe.zhong@rivai.ai
 
From: Robin Dapp
Date: 2023-12-04 20:13
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support highest-number regno overlap for widen ternary vx instructions
> +(define_mode_attr widen_ternop_dest_constraint [
> +  (RVVM8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM1QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM8HI "=vd, vr, vd, vr, vd, vr, ?&vr")
[...]
 
I'm fine with avoiding the overlap but I'm not sure this is
easily maintainable because the constraints don't actually
depend on the mode?  I suppose this is for easy re-use across
different insns but there are only six(?) widening patterns
so we don't even save lines of code by this?
 
I guess I would prefer the normal approach of writing it out
explicitly in the pattern.  Maybe add a different replacement
method like define_subst in the future to simplify such
situations?
 
 
+  "vwmacc<u>.vx\t%0,%z3,%4%p1"
 
Why the z here?  For canonicalization?
 
Regards
Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f97f33f98ee..97a83358c4b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4993,3 +4993,1074 @@ 
   (V256DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")
   (V512DF "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")
 ])
+
+(define_mode_attr widen_ternop_dest_constraint [
+  (RVVM8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF2HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF4HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF2HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF4HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF2SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVMF2SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM8DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM4DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM2DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (RVVM1DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1024QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2048QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4096QI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1024HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2048HI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1024SI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512DI "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1024HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2048HF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1024SF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V1DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V2DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V4DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V8DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V16DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V32DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V64DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V128DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V256DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+  (V512DF "=vd, vr, vd, vr, vd, vr, ?&vr")
+])
+
+(define_mode_attr widen_ternop_mask_constraint [
+  (RVVM8QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF2QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF4QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF8QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF2HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF4HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF2HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF4HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF2SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVMF2SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM8DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM4DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM2DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (RVVM1DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1024QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2048QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4096QI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1024HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2048HI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1024SI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512DI " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1024HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2048HF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1024SF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V1DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V2DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V4DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V8DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V16DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V32DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V64DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V128DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V256DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+  (V512DF " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+])
+
+(define_mode_attr widen_ternop_len_constraint [
+  (RVVM8QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF2QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF4QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF8QI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF2HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF4HI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF2HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF4HF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8SI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4SI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2SI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1SI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF2SI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8SF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4SF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2SF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1SF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVMF2SF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8DI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4DI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2DI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1DI " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM8DF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM4DF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM2DF " rK, rK, rK, rK, rK, rK,   rK")
+  (RVVM1DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V1QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V4QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V8QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V16QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V32QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V64QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V128QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V256QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V512QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1024QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2048QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V4096QI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V4HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V8HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V16HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V32HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V64HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V128HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V256HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V512HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1024HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2048HI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V4SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V8SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V16SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V32SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V64SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V128SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V256SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V512SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1024SI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V2DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V4DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V8DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V16DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V32DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V64DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V128DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V256DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V512DI " rK, rK, rK, rK, rK, rK,   rK")
+  (V1HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V2HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V4HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V8HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V16HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V32HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V64HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V128HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V256HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V512HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V1024HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V2048HF " rK, rK, rK, rK, rK, rK,   rK")
+  (V1SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V2SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V4SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V8SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V16SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V32SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V64SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V128SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V256SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V512SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V1024SF " rK, rK, rK, rK, rK, rK,   rK")
+  (V1DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V2DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V4DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V8DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V16DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V32DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V64DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V128DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V256DF " rK, rK, rK, rK, rK, rK,   rK")
+  (V512DF " rK, rK, rK, rK, rK, rK,   rK")
+])
+
+(define_mode_attr widen_ternop_const_int_constraint [
+  (RVVM8QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF2QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF4QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF8QI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF2HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF4HI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF2HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF4HF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8SI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4SI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2SI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1SI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF2SI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8SF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4SF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2SF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1SF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVMF2SF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8DI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4DI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2DI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1DI "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM8DF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM4DF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM2DF "  i,  i,  i,  i,  i,  i,    i")
+  (RVVM1DF "  i,  i,  i,  i,  i,  i,    i")
+  (V1QI "  i,  i,  i,  i,  i,  i,    i")
+  (V2QI "  i,  i,  i,  i,  i,  i,    i")
+  (V4QI "  i,  i,  i,  i,  i,  i,    i")
+  (V8QI "  i,  i,  i,  i,  i,  i,    i")
+  (V16QI "  i,  i,  i,  i,  i,  i,    i")
+  (V32QI "  i,  i,  i,  i,  i,  i,    i")
+  (V64QI "  i,  i,  i,  i,  i,  i,    i")
+  (V128QI "  i,  i,  i,  i,  i,  i,    i")
+  (V256QI "  i,  i,  i,  i,  i,  i,    i")
+  (V512QI "  i,  i,  i,  i,  i,  i,    i")
+  (V1024QI "  i,  i,  i,  i,  i,  i,    i")
+  (V2048QI "  i,  i,  i,  i,  i,  i,    i")
+  (V4096QI "  i,  i,  i,  i,  i,  i,    i")
+  (V1HI "  i,  i,  i,  i,  i,  i,    i")
+  (V2HI "  i,  i,  i,  i,  i,  i,    i")
+  (V4HI "  i,  i,  i,  i,  i,  i,    i")
+  (V8HI "  i,  i,  i,  i,  i,  i,    i")
+  (V16HI "  i,  i,  i,  i,  i,  i,    i")
+  (V32HI "  i,  i,  i,  i,  i,  i,    i")
+  (V64HI "  i,  i,  i,  i,  i,  i,    i")
+  (V128HI "  i,  i,  i,  i,  i,  i,    i")
+  (V256HI "  i,  i,  i,  i,  i,  i,    i")
+  (V512HI "  i,  i,  i,  i,  i,  i,    i")
+  (V1024HI "  i,  i,  i,  i,  i,  i,    i")
+  (V2048HI "  i,  i,  i,  i,  i,  i,    i")
+  (V1SI "  i,  i,  i,  i,  i,  i,    i")
+  (V2SI "  i,  i,  i,  i,  i,  i,    i")
+  (V4SI "  i,  i,  i,  i,  i,  i,    i")
+  (V8SI "  i,  i,  i,  i,  i,  i,    i")
+  (V16SI "  i,  i,  i,  i,  i,  i,    i")
+  (V32SI "  i,  i,  i,  i,  i,  i,    i")
+  (V64SI "  i,  i,  i,  i,  i,  i,    i")
+  (V128SI "  i,  i,  i,  i,  i,  i,    i")
+  (V256SI "  i,  i,  i,  i,  i,  i,    i")
+  (V512SI "  i,  i,  i,  i,  i,  i,    i")
+  (V1024SI "  i,  i,  i,  i,  i,  i,    i")
+  (V1DI "  i,  i,  i,  i,  i,  i,    i")
+  (V2DI "  i,  i,  i,  i,  i,  i,    i")
+  (V4DI "  i,  i,  i,  i,  i,  i,    i")
+  (V8DI "  i,  i,  i,  i,  i,  i,    i")
+  (V16DI "  i,  i,  i,  i,  i,  i,    i")
+  (V32DI "  i,  i,  i,  i,  i,  i,    i")
+  (V64DI "  i,  i,  i,  i,  i,  i,    i")
+  (V128DI "  i,  i,  i,  i,  i,  i,    i")
+  (V256DI "  i,  i,  i,  i,  i,  i,    i")
+  (V512DI "  i,  i,  i,  i,  i,  i,    i")
+  (V1HF "  i,  i,  i,  i,  i,  i,    i")
+  (V2HF "  i,  i,  i,  i,  i,  i,    i")
+  (V4HF "  i,  i,  i,  i,  i,  i,    i")
+  (V8HF "  i,  i,  i,  i,  i,  i,    i")
+  (V16HF "  i,  i,  i,  i,  i,  i,    i")
+  (V32HF "  i,  i,  i,  i,  i,  i,    i")
+  (V64HF "  i,  i,  i,  i,  i,  i,    i")
+  (V128HF "  i,  i,  i,  i,  i,  i,    i")
+  (V256HF "  i,  i,  i,  i,  i,  i,    i")
+  (V512HF "  i,  i,  i,  i,  i,  i,    i")
+  (V1024HF "  i,  i,  i,  i,  i,  i,    i")
+  (V2048HF "  i,  i,  i,  i,  i,  i,    i")
+  (V1SF "  i,  i,  i,  i,  i,  i,    i")
+  (V2SF "  i,  i,  i,  i,  i,  i,    i")
+  (V4SF "  i,  i,  i,  i,  i,  i,    i")
+  (V8SF "  i,  i,  i,  i,  i,  i,    i")
+  (V16SF "  i,  i,  i,  i,  i,  i,    i")
+  (V32SF "  i,  i,  i,  i,  i,  i,    i")
+  (V64SF "  i,  i,  i,  i,  i,  i,    i")
+  (V128SF "  i,  i,  i,  i,  i,  i,    i")
+  (V256SF "  i,  i,  i,  i,  i,  i,    i")
+  (V512SF "  i,  i,  i,  i,  i,  i,    i")
+  (V1024SF "  i,  i,  i,  i,  i,  i,    i")
+  (V1DF "  i,  i,  i,  i,  i,  i,    i")
+  (V2DF "  i,  i,  i,  i,  i,  i,    i")
+  (V4DF "  i,  i,  i,  i,  i,  i,    i")
+  (V8DF "  i,  i,  i,  i,  i,  i,    i")
+  (V16DF "  i,  i,  i,  i,  i,  i,    i")
+  (V32DF "  i,  i,  i,  i,  i,  i,    i")
+  (V64DF "  i,  i,  i,  i,  i,  i,    i")
+  (V128DF "  i,  i,  i,  i,  i,  i,    i")
+  (V256DF "  i,  i,  i,  i,  i,  i,    i")
+  (V512DF "  i,  i,  i,  i,  i,  i,    i")
+])
+
+(define_mode_attr widen_ternop_scalar_constraint [
+  (RVVM8QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF2QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF4QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF8QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF2HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF4HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF2HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF4HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF2SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVMF2SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM8DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM4DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM2DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (RVVM1DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1024QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2048QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4096QI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1024HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2048HI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1024SI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512DI " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1024HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2048HF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1024SF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V1DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V2DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V4DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V8DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V16DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V32DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V64DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V128DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V256DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+  (V512DF " rJ, rJ, rJ, rJ, rJ, rJ,   rJ")
+])
+
+(define_mode_attr widen_ternop_fp_scalar_constraint [
+  (RVVM8QI " f, f, f, f, f, f, f")
+  (RVVM4QI " f, f, f, f, f, f, f")
+  (RVVM2QI " f, f, f, f, f, f, f")
+  (RVVM1QI " f, f, f, f, f, f, f")
+  (RVVMF2QI " f, f, f, f, f, f, f")
+  (RVVMF4QI " f, f, f, f, f, f, f")
+  (RVVMF8QI " f, f, f, f, f, f, f")
+  (RVVM8HI " f, f, f, f, f, f, f")
+  (RVVM4HI " f, f, f, f, f, f, f")
+  (RVVM2HI " f, f, f, f, f, f, f")
+  (RVVM1HI " f, f, f, f, f, f, f")
+  (RVVMF2HI " f, f, f, f, f, f, f")
+  (RVVMF4HI " f, f, f, f, f, f, f")
+  (RVVM8HF " f, f, f, f, f, f, f")
+  (RVVM4HF " f, f, f, f, f, f, f")
+  (RVVM2HF " f, f, f, f, f, f, f")
+  (RVVM1HF " f, f, f, f, f, f, f")
+  (RVVMF2HF " f, f, f, f, f, f, f")
+  (RVVMF4HF " f, f, f, f, f, f, f")
+  (RVVM8SI " f, f, f, f, f, f, f")
+  (RVVM4SI " f, f, f, f, f, f, f")
+  (RVVM2SI " f, f, f, f, f, f, f")
+  (RVVM1SI " f, f, f, f, f, f, f")
+  (RVVMF2SI " f, f, f, f, f, f, f")
+  (RVVM8SF " f, f, f, f, f, f, f")
+  (RVVM4SF " f, f, f, f, f, f, f")
+  (RVVM2SF " f, f, f, f, f, f, f")
+  (RVVM1SF " f, f, f, f, f, f, f")
+  (RVVMF2SF " f, f, f, f, f, f, f")
+  (RVVM8DI " f, f, f, f, f, f, f")
+  (RVVM4DI " f, f, f, f, f, f, f")
+  (RVVM2DI " f, f, f, f, f, f, f")
+  (RVVM1DI " f, f, f, f, f, f, f")
+  (RVVM8DF " f, f, f, f, f, f, f")
+  (RVVM4DF " f, f, f, f, f, f, f")
+  (RVVM2DF " f, f, f, f, f, f, f")
+  (RVVM1DF " f, f, f, f, f, f, f")
+  (V1QI " f, f, f, f, f, f, f")
+  (V2QI " f, f, f, f, f, f, f")
+  (V4QI " f, f, f, f, f, f, f")
+  (V8QI " f, f, f, f, f, f, f")
+  (V16QI " f, f, f, f, f, f, f")
+  (V32QI " f, f, f, f, f, f, f")
+  (V64QI " f, f, f, f, f, f, f")
+  (V128QI " f, f, f, f, f, f, f")
+  (V256QI " f, f, f, f, f, f, f")
+  (V512QI " f, f, f, f, f, f, f")
+  (V1024QI " f, f, f, f, f, f, f")
+  (V2048QI " f, f, f, f, f, f, f")
+  (V4096QI " f, f, f, f, f, f, f")
+  (V1HI " f, f, f, f, f, f, f")
+  (V2HI " f, f, f, f, f, f, f")
+  (V4HI " f, f, f, f, f, f, f")
+  (V8HI " f, f, f, f, f, f, f")
+  (V16HI " f, f, f, f, f, f, f")
+  (V32HI " f, f, f, f, f, f, f")
+  (V64HI " f, f, f, f, f, f, f")
+  (V128HI " f, f, f, f, f, f, f")
+  (V256HI " f, f, f, f, f, f, f")
+  (V512HI " f, f, f, f, f, f, f")
+  (V1024HI " f, f, f, f, f, f, f")
+  (V2048HI " f, f, f, f, f, f, f")
+  (V1SI " f, f, f, f, f, f, f")
+  (V2SI " f, f, f, f, f, f, f")
+  (V4SI " f, f, f, f, f, f, f")
+  (V8SI " f, f, f, f, f, f, f")
+  (V16SI " f, f, f, f, f, f, f")
+  (V32SI " f, f, f, f, f, f, f")
+  (V64SI " f, f, f, f, f, f, f")
+  (V128SI " f, f, f, f, f, f, f")
+  (V256SI " f, f, f, f, f, f, f")
+  (V512SI " f, f, f, f, f, f, f")
+  (V1024SI " f, f, f, f, f, f, f")
+  (V1DI " f, f, f, f, f, f, f")
+  (V2DI " f, f, f, f, f, f, f")
+  (V4DI " f, f, f, f, f, f, f")
+  (V8DI " f, f, f, f, f, f, f")
+  (V16DI " f, f, f, f, f, f, f")
+  (V32DI " f, f, f, f, f, f, f")
+  (V64DI " f, f, f, f, f, f, f")
+  (V128DI " f, f, f, f, f, f, f")
+  (V256DI " f, f, f, f, f, f, f")
+  (V512DI " f, f, f, f, f, f, f")
+  (V1HF " f, f, f, f, f, f, f")
+  (V2HF " f, f, f, f, f, f, f")
+  (V4HF " f, f, f, f, f, f, f")
+  (V8HF " f, f, f, f, f, f, f")
+  (V16HF " f, f, f, f, f, f, f")
+  (V32HF " f, f, f, f, f, f, f")
+  (V64HF " f, f, f, f, f, f, f")
+  (V128HF " f, f, f, f, f, f, f")
+  (V256HF " f, f, f, f, f, f, f")
+  (V512HF " f, f, f, f, f, f, f")
+  (V1024HF " f, f, f, f, f, f, f")
+  (V2048HF " f, f, f, f, f, f, f")
+  (V1SF " f, f, f, f, f, f, f")
+  (V2SF " f, f, f, f, f, f, f")
+  (V4SF " f, f, f, f, f, f, f")
+  (V8SF " f, f, f, f, f, f, f")
+  (V16SF " f, f, f, f, f, f, f")
+  (V32SF " f, f, f, f, f, f, f")
+  (V64SF " f, f, f, f, f, f, f")
+  (V128SF " f, f, f, f, f, f, f")
+  (V256SF " f, f, f, f, f, f, f")
+  (V512SF " f, f, f, f, f, f, f")
+  (V1024SF " f, f, f, f, f, f, f")
+  (V1DF " f, f, f, f, f, f, f")
+  (V2DF " f, f, f, f, f, f, f")
+  (V4DF " f, f, f, f, f, f, f")
+  (V8DF " f, f, f, f, f, f, f")
+  (V16DF " f, f, f, f, f, f, f")
+  (V32DF " f, f, f, f, f, f, f")
+  (V64DF " f, f, f, f, f, f, f")
+  (V128DF " f, f, f, f, f, f, f")
+  (V256DF " f, f, f, f, f, f, f")
+  (V512DF " f, f, f, f, f, f, f")
+])
+
+(define_mode_attr widen_ternop_source_constraint [
+  (RVVM8QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF2QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF4QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF8QI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF2HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF4HI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF2HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF4HF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8SI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4SI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2SI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1SI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF2SI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8SF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4SF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2SF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1SF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVMF2SF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8DI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4DI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2DI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1DI "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM8DF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM4DF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM2DF "W21,W21,W42,W42,W84,W84,   vr")
+  (RVVM1DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V1QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V4QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V8QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V16QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V32QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V64QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V128QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V256QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V512QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1024QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2048QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V4096QI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V4HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V8HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V16HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V32HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V64HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V128HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V256HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V512HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1024HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2048HI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V4SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V8SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V16SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V32SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V64SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V128SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V256SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V512SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1024SI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V2DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V4DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V8DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V16DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V32DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V64DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V128DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V256DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V512DI "W21,W21,W42,W42,W84,W84,   vr")
+  (V1HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V2HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V4HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V8HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V16HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V32HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V64HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V128HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V256HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V512HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V1024HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V2048HF "W21,W21,W42,W42,W84,W84,   vr")
+  (V1SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V2SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V4SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V8SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V16SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V32SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V64SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V128SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V256SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V512SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V1024SF "W21,W21,W42,W42,W84,W84,   vr")
+  (V1DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V2DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V4DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V8DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V16DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V32DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V64DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V128DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V256DF "W21,W21,W42,W42,W84,W84,   vr")
+  (V512DF "W21,W21,W42,W42,W84,W84,   vr")
+])
+
+(define_mode_attr widen_ternop_merge_constraint [
+  (RVVM8QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF2QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF4QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF8QI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF2HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF4HI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF2HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF4HF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8SI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4SI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2SI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1SI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF2SI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8SF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4SF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2SF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1SF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVMF2SF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8DI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4DI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2DI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1DI "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM8DF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM4DF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM2DF "  0,  0,  0,  0,  0,  0,    0")
+  (RVVM1DF "  0,  0,  0,  0,  0,  0,    0")
+  (V1QI "  0,  0,  0,  0,  0,  0,    0")
+  (V2QI "  0,  0,  0,  0,  0,  0,    0")
+  (V4QI "  0,  0,  0,  0,  0,  0,    0")
+  (V8QI "  0,  0,  0,  0,  0,  0,    0")
+  (V16QI "  0,  0,  0,  0,  0,  0,    0")
+  (V32QI "  0,  0,  0,  0,  0,  0,    0")
+  (V64QI "  0,  0,  0,  0,  0,  0,    0")
+  (V128QI "  0,  0,  0,  0,  0,  0,    0")
+  (V256QI "  0,  0,  0,  0,  0,  0,    0")
+  (V512QI "  0,  0,  0,  0,  0,  0,    0")
+  (V1024QI "  0,  0,  0,  0,  0,  0,    0")
+  (V2048QI "  0,  0,  0,  0,  0,  0,    0")
+  (V4096QI "  0,  0,  0,  0,  0,  0,    0")
+  (V1HI "  0,  0,  0,  0,  0,  0,    0")
+  (V2HI "  0,  0,  0,  0,  0,  0,    0")
+  (V4HI "  0,  0,  0,  0,  0,  0,    0")
+  (V8HI "  0,  0,  0,  0,  0,  0,    0")
+  (V16HI "  0,  0,  0,  0,  0,  0,    0")
+  (V32HI "  0,  0,  0,  0,  0,  0,    0")
+  (V64HI "  0,  0,  0,  0,  0,  0,    0")
+  (V128HI "  0,  0,  0,  0,  0,  0,    0")
+  (V256HI "  0,  0,  0,  0,  0,  0,    0")
+  (V512HI "  0,  0,  0,  0,  0,  0,    0")
+  (V1024HI "  0,  0,  0,  0,  0,  0,    0")
+  (V2048HI "  0,  0,  0,  0,  0,  0,    0")
+  (V1SI "  0,  0,  0,  0,  0,  0,    0")
+  (V2SI "  0,  0,  0,  0,  0,  0,    0")
+  (V4SI "  0,  0,  0,  0,  0,  0,    0")
+  (V8SI "  0,  0,  0,  0,  0,  0,    0")
+  (V16SI "  0,  0,  0,  0,  0,  0,    0")
+  (V32SI "  0,  0,  0,  0,  0,  0,    0")
+  (V64SI "  0,  0,  0,  0,  0,  0,    0")
+  (V128SI "  0,  0,  0,  0,  0,  0,    0")
+  (V256SI "  0,  0,  0,  0,  0,  0,    0")
+  (V512SI "  0,  0,  0,  0,  0,  0,    0")
+  (V1024SI "  0,  0,  0,  0,  0,  0,    0")
+  (V1DI "  0,  0,  0,  0,  0,  0,    0")
+  (V2DI "  0,  0,  0,  0,  0,  0,    0")
+  (V4DI "  0,  0,  0,  0,  0,  0,    0")
+  (V8DI "  0,  0,  0,  0,  0,  0,    0")
+  (V16DI "  0,  0,  0,  0,  0,  0,    0")
+  (V32DI "  0,  0,  0,  0,  0,  0,    0")
+  (V64DI "  0,  0,  0,  0,  0,  0,    0")
+  (V128DI "  0,  0,  0,  0,  0,  0,    0")
+  (V256DI "  0,  0,  0,  0,  0,  0,    0")
+  (V512DI "  0,  0,  0,  0,  0,  0,    0")
+  (V1HF "  0,  0,  0,  0,  0,  0,    0")
+  (V2HF "  0,  0,  0,  0,  0,  0,    0")
+  (V4HF "  0,  0,  0,  0,  0,  0,    0")
+  (V8HF "  0,  0,  0,  0,  0,  0,    0")
+  (V16HF "  0,  0,  0,  0,  0,  0,    0")
+  (V32HF "  0,  0,  0,  0,  0,  0,    0")
+  (V64HF "  0,  0,  0,  0,  0,  0,    0")
+  (V128HF "  0,  0,  0,  0,  0,  0,    0")
+  (V256HF "  0,  0,  0,  0,  0,  0,    0")
+  (V512HF "  0,  0,  0,  0,  0,  0,    0")
+  (V1024HF "  0,  0,  0,  0,  0,  0,    0")
+  (V2048HF "  0,  0,  0,  0,  0,  0,    0")
+  (V1SF "  0,  0,  0,  0,  0,  0,    0")
+  (V2SF "  0,  0,  0,  0,  0,  0,    0")
+  (V4SF "  0,  0,  0,  0,  0,  0,    0")
+  (V8SF "  0,  0,  0,  0,  0,  0,    0")
+  (V16SF "  0,  0,  0,  0,  0,  0,    0")
+  (V32SF "  0,  0,  0,  0,  0,  0,    0")
+  (V64SF "  0,  0,  0,  0,  0,  0,    0")
+  (V128SF "  0,  0,  0,  0,  0,  0,    0")
+  (V256SF "  0,  0,  0,  0,  0,  0,    0")
+  (V512SF "  0,  0,  0,  0,  0,  0,    0")
+  (V1024SF "  0,  0,  0,  0,  0,  0,    0")
+  (V1DF "  0,  0,  0,  0,  0,  0,    0")
+  (V2DF "  0,  0,  0,  0,  0,  0,    0")
+  (V4DF "  0,  0,  0,  0,  0,  0,    0")
+  (V8DF "  0,  0,  0,  0,  0,  0,    0")
+  (V16DF "  0,  0,  0,  0,  0,  0,    0")
+  (V32DF "  0,  0,  0,  0,  0,  0,    0")
+  (V64DF "  0,  0,  0,  0,  0,  0,    0")
+  (V128DF "  0,  0,  0,  0,  0,  0,    0")
+  (V256DF "  0,  0,  0,  0,  0,  0,    0")
+  (V512DF "  0,  0,  0,  0,  0,  0,    0")
+])
+
+(define_mode_attr widen_ternop_group_overlap [
+  (RVVM8QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF2QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF4QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF8QI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF2HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF4HI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF2HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF4HF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8SI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4SI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2SI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1SI "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF2SI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8SF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4SF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2SF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1SF "W21,W21,W42,W42,W84,W84,none")
+  (RVVMF2SF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8DI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4DI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2DI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1DI "W21,W21,W42,W42,W84,W84,none")
+  (RVVM8DF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM4DF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM2DF "W21,W21,W42,W42,W84,W84,none")
+  (RVVM1DF "W21,W21,W42,W42,W84,W84,none")
+  (V1QI "W21,W21,W42,W42,W84,W84,none")
+  (V2QI "W21,W21,W42,W42,W84,W84,none")
+  (V4QI "W21,W21,W42,W42,W84,W84,none")
+  (V8QI "W21,W21,W42,W42,W84,W84,none")
+  (V16QI "W21,W21,W42,W42,W84,W84,none")
+  (V32QI "W21,W21,W42,W42,W84,W84,none")
+  (V64QI "W21,W21,W42,W42,W84,W84,none")
+  (V128QI "W21,W21,W42,W42,W84,W84,none")
+  (V256QI "W21,W21,W42,W42,W84,W84,none")
+  (V512QI "W21,W21,W42,W42,W84,W84,none")
+  (V1024QI "W21,W21,W42,W42,W84,W84,none")
+  (V2048QI "W21,W21,W42,W42,W84,W84,none")
+  (V4096QI "W21,W21,W42,W42,W84,W84,none")
+  (V1HI "W21,W21,W42,W42,W84,W84,none")
+  (V2HI "W21,W21,W42,W42,W84,W84,none")
+  (V4HI "W21,W21,W42,W42,W84,W84,none")
+  (V8HI "W21,W21,W42,W42,W84,W84,none")
+  (V16HI "W21,W21,W42,W42,W84,W84,none")
+  (V32HI "W21,W21,W42,W42,W84,W84,none")
+  (V64HI "W21,W21,W42,W42,W84,W84,none")
+  (V128HI "W21,W21,W42,W42,W84,W84,none")
+  (V256HI "W21,W21,W42,W42,W84,W84,none")
+  (V512HI "W21,W21,W42,W42,W84,W84,none")
+  (V1024HI "W21,W21,W42,W42,W84,W84,none")
+  (V2048HI "W21,W21,W42,W42,W84,W84,none")
+  (V1SI "W21,W21,W42,W42,W84,W84,none")
+  (V2SI "W21,W21,W42,W42,W84,W84,none")
+  (V4SI "W21,W21,W42,W42,W84,W84,none")
+  (V8SI "W21,W21,W42,W42,W84,W84,none")
+  (V16SI "W21,W21,W42,W42,W84,W84,none")
+  (V32SI "W21,W21,W42,W42,W84,W84,none")
+  (V64SI "W21,W21,W42,W42,W84,W84,none")
+  (V128SI "W21,W21,W42,W42,W84,W84,none")
+  (V256SI "W21,W21,W42,W42,W84,W84,none")
+  (V512SI "W21,W21,W42,W42,W84,W84,none")
+  (V1024SI "W21,W21,W42,W42,W84,W84,none")
+  (V1DI "W21,W21,W42,W42,W84,W84,none")
+  (V2DI "W21,W21,W42,W42,W84,W84,none")
+  (V4DI "W21,W21,W42,W42,W84,W84,none")
+  (V8DI "W21,W21,W42,W42,W84,W84,none")
+  (V16DI "W21,W21,W42,W42,W84,W84,none")
+  (V32DI "W21,W21,W42,W42,W84,W84,none")
+  (V64DI "W21,W21,W42,W42,W84,W84,none")
+  (V128DI "W21,W21,W42,W42,W84,W84,none")
+  (V256DI "W21,W21,W42,W42,W84,W84,none")
+  (V512DI "W21,W21,W42,W42,W84,W84,none")
+  (V1HF "W21,W21,W42,W42,W84,W84,none")
+  (V2HF "W21,W21,W42,W42,W84,W84,none")
+  (V4HF "W21,W21,W42,W42,W84,W84,none")
+  (V8HF "W21,W21,W42,W42,W84,W84,none")
+  (V16HF "W21,W21,W42,W42,W84,W84,none")
+  (V32HF "W21,W21,W42,W42,W84,W84,none")
+  (V64HF "W21,W21,W42,W42,W84,W84,none")
+  (V128HF "W21,W21,W42,W42,W84,W84,none")
+  (V256HF "W21,W21,W42,W42,W84,W84,none")
+  (V512HF "W21,W21,W42,W42,W84,W84,none")
+  (V1024HF "W21,W21,W42,W42,W84,W84,none")
+  (V2048HF "W21,W21,W42,W42,W84,W84,none")
+  (V1SF "W21,W21,W42,W42,W84,W84,none")
+  (V2SF "W21,W21,W42,W42,W84,W84,none")
+  (V4SF "W21,W21,W42,W42,W84,W84,none")
+  (V8SF "W21,W21,W42,W42,W84,W84,none")
+  (V16SF "W21,W21,W42,W42,W84,W84,none")
+  (V32SF "W21,W21,W42,W42,W84,W84,none")
+  (V64SF "W21,W21,W42,W42,W84,W84,none")
+  (V128SF "W21,W21,W42,W42,W84,W84,none")
+  (V256SF "W21,W21,W42,W42,W84,W84,none")
+  (V512SF "W21,W21,W42,W42,W84,W84,none")
+  (V1024SF "W21,W21,W42,W42,W84,W84,none")
+  (V1DF "W21,W21,W42,W42,W84,W84,none")
+  (V2DF "W21,W21,W42,W42,W84,W84,none")
+  (V4DF "W21,W21,W42,W42,W84,W84,none")
+  (V8DF "W21,W21,W42,W42,W84,W84,none")
+  (V16DF "W21,W21,W42,W42,W84,W84,none")
+  (V32DF "W21,W21,W42,W42,W84,W84,none")
+  (V64DF "W21,W21,W42,W42,W84,W84,none")
+  (V128DF "W21,W21,W42,W42,W84,W84,none")
+  (V256DF "W21,W21,W42,W42,W84,W84,none")
+  (V512DF "W21,W21,W42,W42,W84,W84,none")
+])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 72cf3553e45..8970f7029b3 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5866,29 +5866,30 @@ 
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                    "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                   "<widen_ternop_dest_constraint>")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
-	     (match_operand 5 "vector_length_operand"                "   rK")
-	     (match_operand 6 "const_int_operand"                    "    i")
-	     (match_operand 7 "const_int_operand"                    "    i")
-	     (match_operand 8 "const_int_operand"                    "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"             "<widen_ternop_mask_constraint>")
+	     (match_operand 5 "vector_length_operand"                "<widen_ternop_len_constraint>")
+	     (match_operand 6 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
+	     (match_operand 7 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
+	     (match_operand 8 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus:VWEXTI
 	    (mult:VWEXTI
 	      (any_extend:VWEXTI
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	          (match_operand:<VSUBEL> 3 "reg_or_0_operand"       "<widen_ternop_scalar_constraint>")))
 	      (any_extend:VWEXTI
-	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	    (match_operand:VWEXTI 2 "register_operand"               "    0"))
+	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "<widen_ternop_source_constraint>")))
+	    (match_operand:VWEXTI 2 "register_operand"               "<widen_ternop_merge_constraint>"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
-  "vwmacc<u>.vx\t%0,%3,%4%p1"
+  "vwmacc<u>.vx\t%0,%z3,%4%p1"
   [(set_attr "type" "viwmuladd")
-   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")
+   (set_attr "group_overlap" "<widen_ternop_group_overlap>")])
 
 (define_insn "@pred_widen_mul_plussu<mode>"
   [(set (match_operand:VWEXTI 0 "register_operand"                    "=&vr")
@@ -5915,54 +5916,56 @@ 
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                    "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                    "<widen_ternop_dest_constraint>")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
-	     (match_operand 5 "vector_length_operand"                "   rK")
-	     (match_operand 6 "const_int_operand"                    "    i")
-	     (match_operand 7 "const_int_operand"                    "    i")
-	     (match_operand 8 "const_int_operand"                    "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"              "<widen_ternop_mask_constraint>")
+	     (match_operand 5 "vector_length_operand"                 "<widen_ternop_len_constraint>")
+	     (match_operand 6 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
+	     (match_operand 7 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
+	     (match_operand 8 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus:VWEXTI
 	    (mult:VWEXTI
 	      (sign_extend:VWEXTI
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	          (match_operand:<VSUBEL> 3 "reg_or_0_operand"        "<widen_ternop_scalar_constraint>")))
 	      (zero_extend:VWEXTI
-	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	    (match_operand:VWEXTI 2 "register_operand"               "    0"))
+	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand"  "<widen_ternop_source_constraint>")))
+	    (match_operand:VWEXTI 2 "register_operand"                "<widen_ternop_merge_constraint>"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
-  "vwmaccsu.vx\t%0,%3,%4%p1"
+  "vwmaccsu.vx\t%0,%z3,%4%p1"
   [(set_attr "type" "viwmuladd")
-   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")
+   (set_attr "group_overlap" "<widen_ternop_group_overlap>")])
 
 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                    "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                    "<widen_ternop_dest_constraint>")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
-	     (match_operand 5 "vector_length_operand"                "   rK")
-	     (match_operand 6 "const_int_operand"                    "    i")
-	     (match_operand 7 "const_int_operand"                    "    i")
-	     (match_operand 8 "const_int_operand"                    "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"              "<widen_ternop_mask_constraint>")
+	     (match_operand 5 "vector_length_operand"                 "<widen_ternop_len_constraint>")
+	     (match_operand 6 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
+	     (match_operand 7 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
+	     (match_operand 8 "const_int_operand"                     "<widen_ternop_const_int_constraint>")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus:VWEXTI
 	    (mult:VWEXTI
 	      (zero_extend:VWEXTI
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	          (match_operand:<VSUBEL> 3 "reg_or_0_operand"       "<widen_ternop_scalar_constraint>")))
 	      (sign_extend:VWEXTI
-	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	    (match_operand:VWEXTI 2 "register_operand"               "    0"))
+	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "<widen_ternop_source_constraint>")))
+	    (match_operand:VWEXTI 2 "register_operand"               "<widen_ternop_merge_constraint>"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
-  "vwmaccus.vx\t%0,%3,%4%p1"
+  "vwmaccus.vx\t%0,%z3,%4%p1"
   [(set_attr "type" "viwmuladd")
-   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")
+   (set_attr "group_overlap" "<widen_ternop_group_overlap>")])
 
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated BOOL mask operations
@@ -7181,15 +7184,15 @@ 
 	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
 
 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
-  [(set (match_operand:VWEXTF 0 "register_operand"                    "=&vr")
+  [(set (match_operand:VWEXTF 0 "register_operand"                    "<widen_ternop_dest_constraint>")
 	(if_then_else:VWEXTF
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1")
-	     (match_operand 5 "vector_length_operand"                "   rK")
-	     (match_operand 6 "const_int_operand"                    "    i")
-	     (match_operand 7 "const_int_operand"                    "    i")
-	     (match_operand 8 "const_int_operand"                    "    i")
-	     (match_operand 9 "const_int_operand"                    "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"             "<widen_ternop_mask_constraint>")
+	     (match_operand 5 "vector_length_operand"                "<widen_ternop_len_constraint>")
+	     (match_operand 6 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
+	     (match_operand 7 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
+	     (match_operand 8 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
+	     (match_operand 9 "const_int_operand"                    "<widen_ternop_const_int_constraint>")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)
 	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
@@ -7197,17 +7200,18 @@ 
 	    (mult:VWEXTF
 	      (float_extend:VWEXTF
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    f")))
+	          (match_operand:<VSUBEL> 3 "register_operand"       "<widen_ternop_fp_scalar_constraint>")))
 	      (float_extend:VWEXTF
-	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	    (match_operand:VWEXTF 2 "register_operand"               "    0"))
+	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "<widen_ternop_source_constraint>")))
+	    (match_operand:VWEXTF 2 "register_operand"               "<widen_ternop_merge_constraint>"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
   "vfw<macc_msac>.vf\t%0,%3,%4%p1"
   [(set_attr "type" "vfwmuladd")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set (attr "frm_mode")
-	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+   (set_attr "group_overlap" "<widen_ternop_group_overlap>")])
 
 (define_insn "@pred_widen_mul_neg_<optab><mode>"
   [(set (match_operand:VWEXTF 0 "register_operand"                      "=&vr")
@@ -7239,15 +7243,15 @@ 
 	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
 
 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
-  [(set (match_operand:VWEXTF 0 "register_operand"                      "=&vr")
+  [(set (match_operand:VWEXTF 0 "register_operand"                      "<widen_ternop_dest_constraint>")
 	(if_then_else:VWEXTF
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"               "vmWc1")
-	     (match_operand 5 "vector_length_operand"                  "   rK")
-	     (match_operand 6 "const_int_operand"                      "    i")
-	     (match_operand 7 "const_int_operand"                      "    i")
-	     (match_operand 8 "const_int_operand"                      "    i")
-	     (match_operand 9 "const_int_operand"                      "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"               "<widen_ternop_mask_constraint>")
+	     (match_operand 5 "vector_length_operand"                  "<widen_ternop_len_constraint>")
+	     (match_operand 6 "const_int_operand"                      "<widen_ternop_const_int_constraint>")
+	     (match_operand 7 "const_int_operand"                      "<widen_ternop_const_int_constraint>")
+	     (match_operand 8 "const_int_operand"                      "<widen_ternop_const_int_constraint>")
+	     (match_operand 9 "const_int_operand"                      "<widen_ternop_const_int_constraint>")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)
 	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
@@ -7256,17 +7260,18 @@ 
 	      (mult:VWEXTF
 	        (float_extend:VWEXTF
 	          (vec_duplicate:<V_DOUBLE_TRUNC>
-	            (match_operand:<VSUBEL> 3 "register_operand"       "    f")))
+	            (match_operand:<VSUBEL> 3 "register_operand"       "<widen_ternop_fp_scalar_constraint>")))
 	        (float_extend:VWEXTF
-	          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr"))))
-	    (match_operand:VWEXTF 2 "register_operand"                 "    0"))
+	          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "<widen_ternop_source_constraint>"))))
+	    (match_operand:VWEXTF 2 "register_operand"                 "<widen_ternop_merge_constraint>"))
 	  (match_dup 2)))]
   "TARGET_VECTOR"
   "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
   [(set_attr "type" "vfwmuladd")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set (attr "frm_mode")
-	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+	(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+   (set_attr "group_overlap" "<widen_ternop_group_overlap>")])
 
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated floating-point comparison operations
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
new file mode 100644
index 00000000000..6337ff875fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
@@ -0,0 +1,103 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out)
+{
+  vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+  vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+  vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+  vint16m2_t result = __riscv_vwmacc_vx_i16m2 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo2 (void *in, void *out)
+{
+  vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+  vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+  vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+  vint16m4_t result = __riscv_vwmacc_vx_i16m4 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo3 (void *in, void *out)
+{
+  vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+  vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+  vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+  vint16m8_t result = __riscv_vwmacc_vx_i16m8 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+void
+foo4 (void *in, void *out)
+{
+  vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+  vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+  vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+  vint16m2_t result = __riscv_vwmaccus_vx_i16m2 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo5 (void *in, void *out)
+{
+  vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+  vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+  vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+  vint16m4_t result = __riscv_vwmaccus_vx_i16m4 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo6 (void *in, void *out)
+{
+  vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+  vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+  vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+  vint16m8_t result = __riscv_vwmaccus_vx_i16m8 (accum, 16, high_eew8, 4);
+  __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+void
+foo7 (void *in, void *out)
+{
+  vint16m2_t accum = __riscv_vle16_v_i16m2 (in, 4);
+  vint16m1_t high_eew16 = __riscv_vget_v_i16m2_i16m1 (accum, 1);
+  vint8m1_t high_eew8 = __riscv_vreinterpret_v_i16m1_i8m1 (high_eew16);
+  vuint8m1_t high_ueew8 = __riscv_vreinterpret_v_i8m1_u8m1 (high_eew8);
+  vint16m2_t result = __riscv_vwmaccsu_vx_i16m2 (accum, 16, high_ueew8, 4);
+  __riscv_vse16_v_i16m2 (out, result, 4);
+}
+
+void
+foo8 (void *in, void *out)
+{
+  vint16m4_t accum = __riscv_vle16_v_i16m4 (in, 4);
+  vint16m2_t high_eew16 = __riscv_vget_v_i16m4_i16m2 (accum, 1);
+  vint8m2_t high_eew8 = __riscv_vreinterpret_v_i16m2_i8m2 (high_eew16);
+  vuint8m2_t high_ueew8 = __riscv_vreinterpret_v_i8m2_u8m2 (high_eew8);
+  vint16m4_t result = __riscv_vwmaccsu_vx_i16m4 (accum, 16, high_ueew8, 4);
+  __riscv_vse16_v_i16m4 (out, result, 4);
+}
+
+void
+foo9 (void *in, void *out)
+{
+  vint16m8_t accum = __riscv_vle16_v_i16m8 (in, 4);
+  vint16m4_t high_eew16 = __riscv_vget_v_i16m8_i16m4 (accum, 1);
+  vint8m4_t high_eew8 = __riscv_vreinterpret_v_i16m4_i8m4 (high_eew16);
+  vuint8m4_t high_ueew8 = __riscv_vreinterpret_v_i8m4_u8m4 (high_eew8);
+  vint16m8_t result = __riscv_vwmaccsu_vx_i16m8 (accum, 16, high_ueew8, 4);
+  __riscv_vse16_v_i16m8 (out, result, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
new file mode 100644
index 00000000000..7b7d6cc7e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
@@ -0,0 +1,82 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void
+foo (void *in, void *out)
+{
+  vfloat64m2_t accum = __riscv_vle64_v_f64m2 (in, 4);
+  vfloat64m1_t high_eew64 = __riscv_vget_v_f64m2_f64m1 (accum, 1);
+  vint64m1_t high_eew64_i = __riscv_vreinterpret_v_f64m1_i64m1 (high_eew64);
+  vint32m1_t high_eew32_i = __riscv_vreinterpret_v_i64m1_i32m1 (high_eew64_i);
+  vfloat32m1_t high_eew32 = __riscv_vreinterpret_v_i32m1_f32m1 (high_eew32_i);
+  vfloat64m2_t result = __riscv_vfwmacc_vf_f64m2 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m2 (out, result, 4);
+}
+
+void
+foo2 (void *in, void *out)
+{
+  vfloat64m4_t accum = __riscv_vle64_v_f64m4 (in, 4);
+  vfloat64m2_t high_eew64 = __riscv_vget_v_f64m4_f64m2 (accum, 1);
+  vint64m2_t high_eew64_i = __riscv_vreinterpret_v_f64m2_i64m2 (high_eew64);
+  vint32m2_t high_eew32_i = __riscv_vreinterpret_v_i64m2_i32m2 (high_eew64_i);
+  vfloat32m2_t high_eew32 = __riscv_vreinterpret_v_i32m2_f32m2 (high_eew32_i);
+  vfloat64m4_t result = __riscv_vfwmacc_vf_f64m4 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m4 (out, result, 4);
+}
+
+void
+foo3 (void *in, void *out)
+{
+  vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4);
+  vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1);
+  vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64);
+  vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i);
+  vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i);
+  vfloat64m8_t result = __riscv_vfwmacc_vf_f64m8 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m8 (out, result, 4);
+}
+
+void
+foo4 (void *in, void *out)
+{
+  vfloat64m2_t accum = __riscv_vle64_v_f64m2 (in, 4);
+  vfloat64m1_t high_eew64 = __riscv_vget_v_f64m2_f64m1 (accum, 1);
+  vint64m1_t high_eew64_i = __riscv_vreinterpret_v_f64m1_i64m1 (high_eew64);
+  vint32m1_t high_eew32_i = __riscv_vreinterpret_v_i64m1_i32m1 (high_eew64_i);
+  vfloat32m1_t high_eew32 = __riscv_vreinterpret_v_i32m1_f32m1 (high_eew32_i);
+  vfloat64m2_t result = __riscv_vfwnmsac_vf_f64m2 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m2 (out, result, 4);
+}
+
+void
+foo5 (void *in, void *out)
+{
+  vfloat64m4_t accum = __riscv_vle64_v_f64m4 (in, 4);
+  vfloat64m2_t high_eew64 = __riscv_vget_v_f64m4_f64m2 (accum, 1);
+  vint64m2_t high_eew64_i = __riscv_vreinterpret_v_f64m2_i64m2 (high_eew64);
+  vint32m2_t high_eew32_i = __riscv_vreinterpret_v_i64m2_i32m2 (high_eew64_i);
+  vfloat32m2_t high_eew32 = __riscv_vreinterpret_v_i32m2_f32m2 (high_eew32_i);
+  vfloat64m4_t result = __riscv_vfwnmsac_vf_f64m4 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m4 (out, result, 4);
+}
+
+void
+foo6 (void *in, void *out)
+{
+  vfloat64m8_t accum = __riscv_vle64_v_f64m8 (in, 4);
+  vfloat64m4_t high_eew64 = __riscv_vget_v_f64m8_f64m4 (accum, 1);
+  vint64m4_t high_eew64_i = __riscv_vreinterpret_v_f64m4_i64m4 (high_eew64);
+  vint32m4_t high_eew32_i = __riscv_vreinterpret_v_i64m4_i32m4 (high_eew64_i);
+  vfloat32m4_t high_eew32 = __riscv_vreinterpret_v_i32m4_f32m4 (high_eew32_i);
+  vfloat64m8_t result = __riscv_vfwnmsac_vf_f64m8 (accum, 64, high_eew32, 4);
+  __riscv_vse64_v_f64m8 (out, result, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */