diff mbox series

[PATCHv9,5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk

Message ID 20221114230217.202634-5-dinguyen@kernel.org
State New
Headers
Series [PATCHv9,1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" |

Commit Message

Dinh Nguyen Nov. 14, 2022, 11:02 p.m. UTC 
  Now that the SDMMC driver supports setting the clk-phase, we can remove
the need to do it in the clock driver.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v9: no changes
v8: no changes
v7: add acked-by
v6: remove unused clk_phase in clk-gate.c
v5: new
---
 drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------
 drivers/clk/socfpga/clk-gate.c     | 61 ---------------------------
 drivers/clk/socfpga/clk.h          |  1 -
 3 files changed, 130 deletions(-)

Comments

Ulf Hansson Nov. 18, 2022, 9:45 a.m. UTC | #1 
On Tue, 15 Nov 2022 at 00:02, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
> Now that the SDMMC driver supports setting the clk-phase, we can remove
> the need to do it in the clock driver.
>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Applied for next, thanks!

Kind regards
Uffe


> ---
> v9: no changes
> v8: no changes
> v7: add acked-by
> v6: remove unused clk_phase in clk-gate.c
> v5: new
> ---
>  drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------
>  drivers/clk/socfpga/clk-gate.c     | 61 ---------------------------
>  drivers/clk/socfpga/clk.h          |  1 -
>  3 files changed, 130 deletions(-)
>
> diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
> index 738c53391e39..7cdf2f07c79b 100644
> --- a/drivers/clk/socfpga/clk-gate-a10.c
> +++ b/drivers/clk/socfpga/clk-gate-a10.c
> @@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
>         return parent_rate / div;
>  }
>
> -static int socfpga_clk_prepare(struct clk_hw *hwclk)
> -{
> -       struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> -       int i;
> -       u32 hs_timing;
> -       u32 clk_phase[2];
> -
> -       if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> -               for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
> -                       switch (socfpgaclk->clk_phase[i]) {
> -                       case 0:
> -                               clk_phase[i] = 0;
> -                               break;
> -                       case 45:
> -                               clk_phase[i] = 1;
> -                               break;
> -                       case 90:
> -                               clk_phase[i] = 2;
> -                               break;
> -                       case 135:
> -                               clk_phase[i] = 3;
> -                               break;
> -                       case 180:
> -                               clk_phase[i] = 4;
> -                               break;
> -                       case 225:
> -                               clk_phase[i] = 5;
> -                               break;
> -                       case 270:
> -                               clk_phase[i] = 6;
> -                               break;
> -                       case 315:
> -                               clk_phase[i] = 7;
> -                               break;
> -                       default:
> -                               clk_phase[i] = 0;
> -                               break;
> -                       }
> -               }
> -
> -               hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
> -               if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
> -                       regmap_write(socfpgaclk->sys_mgr_base_addr,
> -                                    SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
> -               else
> -                       pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
> -                                       __func__);
> -       }
> -       return 0;
> -}
> -
>  static struct clk_ops gateclk_ops = {
> -       .prepare = socfpga_clk_prepare,
>         .recalc_rate = socfpga_gate_clk_recalc_rate,
>  };
>
> @@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
>  {
>         u32 clk_gate[2];
>         u32 div_reg[3];
> -       u32 clk_phase[2];
>         u32 fixed_div;
>         struct clk_hw *hw_clk;
>         struct socfpga_gate_clk *socfpga_clk;
> @@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node,
>                 socfpga_clk->div_reg = NULL;
>         }
>
> -       rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> -       if (!rc) {
> -               socfpga_clk->clk_phase[0] = clk_phase[0];
> -               socfpga_clk->clk_phase[1] = clk_phase[1];
> -
> -               socfpga_clk->sys_mgr_base_addr =
> -                       syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> -               if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
> -                       pr_err("%s: failed to find altr,sys-mgr regmap!\n",
> -                                       __func__);
> -                       kfree(socfpga_clk);
> -                       return;
> -               }
> -       }
> -
>         of_property_read_string(node, "clock-output-names", &clk_name);
>
>         init.name = clk_name;
> diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
> index 53d6e3ec4309..3e347b9e9eff 100644
> --- a/drivers/clk/socfpga/clk-gate.c
> +++ b/drivers/clk/socfpga/clk-gate.c
> @@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
>         return parent_rate / div;
>  }
>
> -static int socfpga_clk_prepare(struct clk_hw *hwclk)
> -{
> -       struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> -       struct regmap *sys_mgr_base_addr;
> -       int i;
> -       u32 hs_timing;
> -       u32 clk_phase[2];
> -
> -       if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
> -               sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> -               if (IS_ERR(sys_mgr_base_addr)) {
> -                       pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
> -                       return -EINVAL;
> -               }
> -
> -               for (i = 0; i < 2; i++) {
> -                       switch (socfpgaclk->clk_phase[i]) {
> -                       case 0:
> -                               clk_phase[i] = 0;
> -                               break;
> -                       case 45:
> -                               clk_phase[i] = 1;
> -                               break;
> -                       case 90:
> -                               clk_phase[i] = 2;
> -                               break;
> -                       case 135:
> -                               clk_phase[i] = 3;
> -                               break;
> -                       case 180:
> -                               clk_phase[i] = 4;
> -                               break;
> -                       case 225:
> -                               clk_phase[i] = 5;
> -                               break;
> -                       case 270:
> -                               clk_phase[i] = 6;
> -                               break;
> -                       case 315:
> -                               clk_phase[i] = 7;
> -                               break;
> -                       default:
> -                               clk_phase[i] = 0;
> -                               break;
> -                       }
> -               }
> -               hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
> -               regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> -                       hs_timing);
> -       }
> -       return 0;
> -}
> -
>  static struct clk_ops gateclk_ops = {
> -       .prepare = socfpga_clk_prepare,
>         .recalc_rate = socfpga_clk_recalc_rate,
>         .get_parent = socfpga_clk_get_parent,
>         .set_parent = socfpga_clk_set_parent,
> @@ -172,7 +118,6 @@ void __init socfpga_gate_init(struct device_node *node)
>  {
>         u32 clk_gate[2];
>         u32 div_reg[3];
> -       u32 clk_phase[2];
>         u32 fixed_div;
>         struct clk_hw *hw_clk;
>         struct socfpga_gate_clk *socfpga_clk;
> @@ -218,12 +163,6 @@ void __init socfpga_gate_init(struct device_node *node)
>                 socfpga_clk->div_reg = NULL;
>         }
>
> -       rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
> -       if (!rc) {
> -               socfpga_clk->clk_phase[0] = clk_phase[0];
> -               socfpga_clk->clk_phase[1] = clk_phase[1];
> -       }
> -
>         of_property_read_string(node, "clock-output-names", &clk_name);
>
>         init.name = clk_name;
> diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
> index d80115fbdd6a..9a2fb2dde5b8 100644
> --- a/drivers/clk/socfpga/clk.h
> +++ b/drivers/clk/socfpga/clk.h
> @@ -50,7 +50,6 @@ struct socfpga_gate_clk {
>         u32 width;      /* only valid if div_reg != 0 */
>         u32 shift;      /* only valid if div_reg != 0 */
>         u32 bypass_shift;      /* only valid if bypass_reg != 0 */
> -       u32 clk_phase[2];
>  };
>
>  struct socfpga_periph_clk {
> --
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 738c53391e39..7cdf2f07c79b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -35,59 +35,7 @@  static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hwclk)
-{
-	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
-	int i;
-	u32 hs_timing;
-	u32 clk_phase[2];
-
-	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-		for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
-			switch (socfpgaclk->clk_phase[i]) {
-			case 0:
-				clk_phase[i] = 0;
-				break;
-			case 45:
-				clk_phase[i] = 1;
-				break;
-			case 90:
-				clk_phase[i] = 2;
-				break;
-			case 135:
-				clk_phase[i] = 3;
-				break;
-			case 180:
-				clk_phase[i] = 4;
-				break;
-			case 225:
-				clk_phase[i] = 5;
-				break;
-			case 270:
-				clk_phase[i] = 6;
-				break;
-			case 315:
-				clk_phase[i] = 7;
-				break;
-			default:
-				clk_phase[i] = 0;
-				break;
-			}
-		}
-
-		hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
-		if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
-			regmap_write(socfpgaclk->sys_mgr_base_addr,
-				     SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
-		else
-			pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
-					__func__);
-	}
-	return 0;
-}
-
 static struct clk_ops gateclk_ops = {
-	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_gate_clk_recalc_rate,
 };
 
@@ -96,7 +44,6 @@  static void __init __socfpga_gate_init(struct device_node *node,
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
-	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -136,21 +83,6 @@  static void __init __socfpga_gate_init(struct device_node *node,
 		socfpga_clk->div_reg = NULL;
 	}
 
-	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-	if (!rc) {
-		socfpga_clk->clk_phase[0] = clk_phase[0];
-		socfpga_clk->clk_phase[1] = clk_phase[1];
-
-		socfpga_clk->sys_mgr_base_addr =
-			syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-		if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
-			pr_err("%s: failed to find altr,sys-mgr regmap!\n",
-					__func__);
-			kfree(socfpga_clk);
-			return;
-		}
-	}
-
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 53d6e3ec4309..3e347b9e9eff 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -108,61 +108,7 @@  static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 	return parent_rate / div;
 }
 
-static int socfpga_clk_prepare(struct clk_hw *hwclk)
-{
-	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
-	struct regmap *sys_mgr_base_addr;
-	int i;
-	u32 hs_timing;
-	u32 clk_phase[2];
-
-	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
-		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-		if (IS_ERR(sys_mgr_base_addr)) {
-			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
-			return -EINVAL;
-		}
-
-		for (i = 0; i < 2; i++) {
-			switch (socfpgaclk->clk_phase[i]) {
-			case 0:
-				clk_phase[i] = 0;
-				break;
-			case 45:
-				clk_phase[i] = 1;
-				break;
-			case 90:
-				clk_phase[i] = 2;
-				break;
-			case 135:
-				clk_phase[i] = 3;
-				break;
-			case 180:
-				clk_phase[i] = 4;
-				break;
-			case 225:
-				clk_phase[i] = 5;
-				break;
-			case 270:
-				clk_phase[i] = 6;
-				break;
-			case 315:
-				clk_phase[i] = 7;
-				break;
-			default:
-				clk_phase[i] = 0;
-				break;
-			}
-		}
-		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
-		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
-			hs_timing);
-	}
-	return 0;
-}
-
 static struct clk_ops gateclk_ops = {
-	.prepare = socfpga_clk_prepare,
 	.recalc_rate = socfpga_clk_recalc_rate,
 	.get_parent = socfpga_clk_get_parent,
 	.set_parent = socfpga_clk_set_parent,
@@ -172,7 +118,6 @@  void __init socfpga_gate_init(struct device_node *node)
 {
 	u32 clk_gate[2];
 	u32 div_reg[3];
-	u32 clk_phase[2];
 	u32 fixed_div;
 	struct clk_hw *hw_clk;
 	struct socfpga_gate_clk *socfpga_clk;
@@ -218,12 +163,6 @@  void __init socfpga_gate_init(struct device_node *node)
 		socfpga_clk->div_reg = NULL;
 	}
 
-	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
-	if (!rc) {
-		socfpga_clk->clk_phase[0] = clk_phase[0];
-		socfpga_clk->clk_phase[1] = clk_phase[1];
-	}
-
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
 	init.name = clk_name;
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d80115fbdd6a..9a2fb2dde5b8 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -50,7 +50,6 @@  struct socfpga_gate_clk {
 	u32 width;	/* only valid if div_reg != 0 */
 	u32 shift;	/* only valid if div_reg != 0 */
 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
-	u32 clk_phase[2];
 };
 
 struct socfpga_periph_clk {