diff mbox series

drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg()

Message ID 20231129152230.7931-1-n.zhandarovich@fintech.ru
State New
Headers
Series drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg() |

Commit Message

Nikita Zhandarovich Nov. 29, 2023, 3:22 p.m. UTC 
  While improbable, there may be a chance of hitting integer
overflow when the result of radeon_get_ib_value() gets shifted
left.

Avoid it by casting one of the operands to larger data type (u64).

Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.

Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
---
 drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Christian König Nov. 29, 2023, 3:47 p.m. UTC | #1 
Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
> While improbable, there may be a chance of hitting integer
> overflow when the result of radeon_get_ib_value() gets shifted
> left.
>
> Avoid it by casting one of the operands to larger data type (u64).
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.

Well IIRC cb_color_bo_offset is just 32bits anyway, so this doesn't 
change anything.

Regards,
Christian.

>
> Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
> Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
> ---
>   drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> index 638f861af80f..6cf54a747749 100644
> --- a/drivers/gpu/drm/radeon/r600_cs.c
> +++ b/drivers/gpu/drm/radeon/r600_cs.c
> @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>   			return -EINVAL;
>   		}
>   		tmp = (reg - CB_COLOR0_BASE) / 4;
> -		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
> +		track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
>   		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>   		track->cb_color_base_last[tmp] = ib[idx];
>   		track->cb_color_bo[tmp] = reloc->robj;
> @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>   					"0x%04X\n", reg);
>   			return -EINVAL;
>   		}
> -		track->htile_offset = radeon_get_ib_value(p, idx) << 8;
> +		track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
>   		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>   		track->htile_bo = reloc->robj;
>   		track->db_dirty = true;
Alex Deucher Nov. 29, 2023, 4:03 p.m. UTC | #2 
On Wed, Nov 29, 2023 at 10:47 AM Christian König
<christian.koenig@amd.com> wrote:
>
> Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
> > While improbable, there may be a chance of hitting integer
> > overflow when the result of radeon_get_ib_value() gets shifted
> > left.
> >
> > Avoid it by casting one of the operands to larger data type (u64).
> >
> > Found by Linux Verification Center (linuxtesting.org) with static
> > analysis tool SVACE.
>
> Well IIRC cb_color_bo_offset is just 32bits anyway, so this doesn't
> change anything.

All of the GPU addresses in the structure are u64.  The registers are
32 bits which is why they are 256 byte aligned.  That said, I think
the MC on the chips supported by this code are only 32 bits so we
shouldn't see any addresses greater than 32 bits, but this seems like
good to do from a coding perspective.  Otherwise, we'll keep getting
this patch.

Alex


Alex

>
> Regards,
> Christian.
>
> >
> > Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
> > Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
> > ---
> >   drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> > index 638f861af80f..6cf54a747749 100644
> > --- a/drivers/gpu/drm/radeon/r600_cs.c
> > +++ b/drivers/gpu/drm/radeon/r600_cs.c
> > @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> >                       return -EINVAL;
> >               }
> >               tmp = (reg - CB_COLOR0_BASE) / 4;
> > -             track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
> > +             track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
> >               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
> >               track->cb_color_base_last[tmp] = ib[idx];
> >               track->cb_color_bo[tmp] = reloc->robj;
> > @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
> >                                       "0x%04X\n", reg);
> >                       return -EINVAL;
> >               }
> > -             track->htile_offset = radeon_get_ib_value(p, idx) << 8;
> > +             track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
> >               ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
> >               track->htile_bo = reloc->robj;
> >               track->db_dirty = true;
>
Christian König Nov. 30, 2023, 6:41 a.m. UTC | #3 
Am 29.11.23 um 17:03 schrieb Alex Deucher:
> On Wed, Nov 29, 2023 at 10:47 AM Christian König
> <christian.koenig@amd.com> wrote:
>> Am 29.11.23 um 16:22 schrieb Nikita Zhandarovich:
>>> While improbable, there may be a chance of hitting integer
>>> overflow when the result of radeon_get_ib_value() gets shifted
>>> left.
>>>
>>> Avoid it by casting one of the operands to larger data type (u64).
>>>
>>> Found by Linux Verification Center (linuxtesting.org) with static
>>> analysis tool SVACE.
>> Well IIRC cb_color_bo_offset is just 32bits anyway, so this doesn't
>> change anything.
> All of the GPU addresses in the structure are u64.  The registers are
> 32 bits which is why they are 256 byte aligned.  That said, I think
> the MC on the chips supported by this code are only 32 bits so we
> shouldn't see any addresses greater than 32 bits, but this seems like
> good to do from a coding perspective.  Otherwise, we'll keep getting
> this patch.

Just double checked it, in evergreen_cs_track the fields are just 
32bits, but in r600_cs_track they are 64bits.

No idea if we every used the full address space, but it's probably a 
good point to merge it just to silence the static checker warning.

Christian.

>
> Alex
>
>
> Alex
>
>> Regards,
>> Christian.
>>
>>> Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
>>> Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
>>> ---
>>>    drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
>>> index 638f861af80f..6cf54a747749 100644
>>> --- a/drivers/gpu/drm/radeon/r600_cs.c
>>> +++ b/drivers/gpu/drm/radeon/r600_cs.c
>>> @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>>>                        return -EINVAL;
>>>                }
>>>                tmp = (reg - CB_COLOR0_BASE) / 4;
>>> -             track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
>>> +             track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
>>>                ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>>>                track->cb_color_base_last[tmp] = ib[idx];
>>>                track->cb_color_bo[tmp] = reloc->robj;
>>> @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>>>                                        "0x%04X\n", reg);
>>>                        return -EINVAL;
>>>                }
>>> -             track->htile_offset = radeon_get_ib_value(p, idx) << 8;
>>> +             track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
>>>                ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>>>                track->htile_bo = reloc->robj;
>>>                track->db_dirty = true;
Alex Deucher Nov. 30, 2023, 5:06 p.m. UTC | #4 
Applied.  Thanks!

On Wed, Nov 29, 2023 at 10:28 AM Nikita Zhandarovich
<n.zhandarovich@fintech.ru> wrote:
>
> While improbable, there may be a chance of hitting integer
> overflow when the result of radeon_get_ib_value() gets shifted
> left.
>
> Avoid it by casting one of the operands to larger data type (u64).
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.
>
> Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
> Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
> ---
>  drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
> index 638f861af80f..6cf54a747749 100644
> --- a/drivers/gpu/drm/radeon/r600_cs.c
> +++ b/drivers/gpu/drm/radeon/r600_cs.c
> @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>                         return -EINVAL;
>                 }
>                 tmp = (reg - CB_COLOR0_BASE) / 4;
> -               track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
> +               track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
>                 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>                 track->cb_color_base_last[tmp] = ib[idx];
>                 track->cb_color_bo[tmp] = reloc->robj;
> @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
>                                         "0x%04X\n", reg);
>                         return -EINVAL;
>                 }
> -               track->htile_offset = radeon_get_ib_value(p, idx) << 8;
> +               track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
>                 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
>                 track->htile_bo = reloc->robj;
>                 track->db_dirty = true;
> --
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 638f861af80f..6cf54a747749 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1275,7 +1275,7 @@  static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 			return -EINVAL;
 		}
 		tmp = (reg - CB_COLOR0_BASE) / 4;
-		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
+		track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
 		track->cb_color_base_last[tmp] = ib[idx];
 		track->cb_color_bo[tmp] = reloc->robj;
@@ -1302,7 +1302,7 @@  static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
 					"0x%04X\n", reg);
 			return -EINVAL;
 		}
-		track->htile_offset = radeon_get_ib_value(p, idx) << 8;
+		track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
 		ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
 		track->htile_bo = reloc->robj;
 		track->db_dirty = true;