[4/5,BINUTILS] aarch64: Add new AT system instructions.
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Commit Message
HI,
This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
Regression tested for aarch64-none-elf target and found
no regressions.
Ok for binutils-master?
Regards,
Srinath.
Comments
On 16.11.2023 12:39, Srinath Parvathaneni wrote:
> This patch adds the permission model enhancement and memory
> attribute index enhancement features and their corresponding
> system registers in AArch64 assembler.
> Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
> Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
> Memory Attribute Index Enhancement (FEAT_AIE)
> Extension to Translation Control Registers (FEAT_TCR2)
With the public documentation not (yet) mentioning these registers
(and you also not providing references to, perhaps, incremental
documentation which is going to be folded into the ARM), it's
pretty hard to judge whether what might look like a typo actually
is one. In particular in
@@ -556,6 +560,10 @@
SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
the EL2 and EL3 values using 1s where the EL1 and EL12 values use 2s
looks somewhat suspicious. No similar inconsistency exists for AMAIR2,
for example.
Jan
@@ -24,3 +24,6 @@
.*: Error: selected processor does not support system register name 'pfar_el1'
.*: Error: selected processor does not support system register name 'pfar_el2'
.*: Error: selected processor does not support system register name 'pfar_el12'
+.*: Error: selected processor does not support system register name 's1e1a'
+.*: Error: selected processor does not support system register name 's1e2a'
+.*: Error: selected processor does not support system register name 's1e3a'
@@ -31,3 +31,6 @@ Disassembly of section \.text:
.*: d51860a0 msr pfar_el1, x0
.*: d51c60a0 msr pfar_el2, x0
.*: d51d60a0 msr pfar_el12, x0
+.*: d5087941 at s1e1a, x1
+.*: d50c7943 at s1e2a, x3
+.*: d50e7945 at s1e3a, x5
@@ -27,3 +27,8 @@
msr PFAR_EL1, x0
msr PFAR_EL2, x0
msr PFAR_EL12, x0
+
+ /* AT. */
+ at s1e1a, x1
+ at s1e2a, x3
+ at s1e3a, x5
@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FGT2,
/* Physical Fault Address. */
AARCH64_FEATURE_PFAR,
+ /* Address Translate Stage 1. */
+ AARCH64_FEATURE_ATS1A,
AARCH64_NUM_FEATURES
};
@@ -245,7 +247,8 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, RASv2) \
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
- | AARCH64_FEATBIT (X, PFAR))
+ | AARCH64_FEATBIT (X, PFAR) \
+ | AARCH64_FEATBIT (X, ATS1A))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
@@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
{ "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
+ { "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};
@@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, THE))
return true;
+ if ((reg_value == CPENS (0, C7, C9, 2)
+ || reg_value == CPENS (4, C7, C9, 2)
+ || reg_value == CPENS (6, C7, C9, 2))
+ && AARCH64_CPU_HAS_FEATURE (features, ATS1A))
+ return true;
+
return false;
}