diff mbox series

[v2,1/2] arm64: dts: ti: k3-am62a-main: Add sdhci0 instance

Message ID 20231030063108.1242981-2-n-yadav@ti.com
State New
Headers
Series Add eMMC support for AM62a SK |

Commit Message

Nitin Yadav Oct. 30, 2023, 6:31 a.m. UTC 
  Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
ITAP values as they are NA in datasheet[0] for lower speed modes.

[0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)

Signed-off-by: Nitin Yadav <n-yadav@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Judith Mendez Nov. 27, 2023, 9:41 p.m. UTC | #1 
On 10/30/23 1:31 AM, Nitin Yadav wrote:
> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
> ITAP values as they are NA in datasheet[0] for lower speed modes.
> 
> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
> 

Minor comment below. All else looks good to me.

Reviewed by: Judith Mendez <jm@ti.com>

> Signed-off-by: Nitin Yadav <n-yadav@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> index de36abb243f1..89b8b7d302cd 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
>   		status = "disabled";
>   	};
>   
> +	sdhci0: mmc@fa10000 {
> +		compatible = "ti,am62-sdhci";
> +		reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
> +		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
> +		clock-names = "clk_ahb", "clk_xin";
> +		assigned-clocks = <&k3_clks 57 6>;
> +		assigned-clock-parents = <&k3_clks 57 8>;
> +		mmc-hs200-1_8v;
> +		ti,trm-icp = <0x2>;
> +		ti,otap-del-sel-legacy = <0x0>;
> +		ti,otap-del-sel-mmc-hs = <0x0>;
> +		ti,otap-del-sel-hs200 = <0x6>;

I am wondering why DDR52 speed mode was not added?

> +		bus-width = <8>;
> +		ti,clkbuf-sel = <0x7>;
> +		status = "disabled";
> +	};
> +
>   	sdhci1: mmc@fa00000 {
>   		compatible = "ti,am62-sdhci";
>   		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;

~ Judith
Nitin Yadav Nov. 28, 2023, 4:39 a.m. UTC | #2 
On 11/28/2023 3:11 AM, Judith Mendez wrote:
> On 10/30/23 1:31 AM, Nitin Yadav wrote:
>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
>> ITAP values as they are NA in datasheet[0] for lower speed modes.
>>
>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>>
> 
> Minor comment below. All else looks good to me.
> 
> Reviewed by: Judith Mendez <jm@ti.com>
> 
>> Signed-off-by: Nitin Yadav <n-yadav@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>>   1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> index de36abb243f1..89b8b7d302cd 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
>>           status = "disabled";
>>       };
>>   +    sdhci0: mmc@fa10000 {
>> +        compatible = "ti,am62-sdhci";
>> +        reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>> +        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> +        power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>> +        clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
>> +        clock-names = "clk_ahb", "clk_xin";
>> +        assigned-clocks = <&k3_clks 57 6>;
>> +        assigned-clock-parents = <&k3_clks 57 8>;
>> +        mmc-hs200-1_8v;
>> +        ti,trm-icp = <0x2>;
>> +        ti,otap-del-sel-legacy = <0x0>;
>> +        ti,otap-del-sel-mmc-hs = <0x0>;
>> +        ti,otap-del-sel-hs200 = <0x6>;
> 
> I am wondering why DDR52 speed mode was not added?
plz refer datasheet. No mention of DDR52 in this revised addition.
> 
>> +        bus-width = <8>;
>> +        ti,clkbuf-sel = <0x7>;
>> +        status = "disabled";
>> +    };
>> +
>>       sdhci1: mmc@fa00000 {
>>           compatible = "ti,am62-sdhci";
>>           reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
> 
> ~ Judith
Judith Mendez Nov. 28, 2023, 7:58 p.m. UTC | #3 
Hi Nitin,

On 11/27/23 10:39 PM, Nitin Yadav wrote:
> 
> 
> On 11/28/2023 3:11 AM, Judith Mendez wrote:
>> On 10/30/23 1:31 AM, Nitin Yadav wrote:
>>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
>>> ITAP values as they are NA in datasheet[0] for lower speed modes.
>>>
>>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>>>
>>
>> Minor comment below. All else looks good to me.
>>
>> Reviewed by: Judith Mendez <jm@ti.com>
>>
>>> Signed-off-by: Nitin Yadav <n-yadav@ti.com>
>>> ---
>>>    arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>>>    1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> index de36abb243f1..89b8b7d302cd 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 {
>>>            status = "disabled";
>>>        };
>>>    +    sdhci0: mmc@fa10000 {
>>> +        compatible = "ti,am62-sdhci";
>>> +        reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>>> +        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>> +        power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>>> +        clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
>>> +        clock-names = "clk_ahb", "clk_xin";
>>> +        assigned-clocks = <&k3_clks 57 6>;
>>> +        assigned-clock-parents = <&k3_clks 57 8>;
>>> +        mmc-hs200-1_8v;
>>> +        ti,trm-icp = <0x2>;
>>> +        ti,otap-del-sel-legacy = <0x0>;
>>> +        ti,otap-del-sel-mmc-hs = <0x0>;
>>> +        ti,otap-del-sel-hs200 = <0x6>;
>>
>> I am wondering why DDR52 speed mode was not added?
> plz refer datasheet. No mention of DDR52 in this revised addition.
I believe it is mentioned in the RIOT, not datasheet.

>>
>>> +        bus-width = <8>;
>>> +        ti,clkbuf-sel = <0x7>;
>>> +        status = "disabled";
>>> +    };
>>> +
>>>        sdhci1: mmc@fa00000 {
>>>            compatible = "ti,am62-sdhci";
>>>            reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
>>
>> ~ Judith
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
index de36abb243f1..89b8b7d302cd 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
@@ -488,6 +488,25 @@  main_gpio1: gpio@601000 {
 		status = "disabled";
 	};
 
+	sdhci0: mmc@fa10000 {
+		compatible = "ti,am62-sdhci";
+		reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+		clock-names = "clk_ahb", "clk_xin";
+		assigned-clocks = <&k3_clks 57 6>;
+		assigned-clock-parents = <&k3_clks 57 8>;
+		mmc-hs200-1_8v;
+		ti,trm-icp = <0x2>;
+		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-mmc-hs = <0x0>;
+		ti,otap-del-sel-hs200 = <0x6>;
+		bus-width = <8>;
+		ti,clkbuf-sel = <0x7>;
+		status = "disabled";
+	};
+
 	sdhci1: mmc@fa00000 {
 		compatible = "ti,am62-sdhci";
 		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;