Message ID | 20231030063108.1242981-2-n-yadav@ti.com |
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State | New |
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[2620:137:e000::3:2]) by mx.google.com with ESMTPS id y11-20020a62ce0b000000b0068895dea43csi4433143pfg.78.2023.10.29.23.32.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Oct 2023 23:32:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dtVxkZGI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 014BE8053C64; Sun, 29 Oct 2023 23:32:15 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231638AbjJ3GcA (ORCPT <rfc822;chrisjones.unixmen@gmail.com> + 32 others); Mon, 30 Oct 2023 02:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231426AbjJ3Gbv (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 30 Oct 2023 02:31:51 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25D39135; Sun, 29 Oct 2023 23:31:24 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 39U6VBkD083087; Mon, 30 Oct 2023 01:31:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1698647471; bh=wRqcz0GeUPoqwWeMEBPoeB3CSHBuUPhuPWYUDN0JZnQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dtVxkZGIAq1c0C5XLxQAyC/zkfDhLMGvJWrFKA+066/eI0N/Bgjryru8fNjDilnD+ VrescrTgOdVwmu9l0mW8iCFiVFkhFgQTZmwTsl0sRDlH+OE16I4AZRtnihIp0hKbS6 CIXhlYaxI3RcPK8/OzRZ9Cf9WOQxHVzgr/T69vfo= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 39U6VBT6009169 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 30 Oct 2023 01:31:11 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 30 Oct 2023 01:31:11 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 30 Oct 2023 01:31:11 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 39U6VAe4003179; Mon, 30 Oct 2023 01:31:10 -0500 From: Nitin Yadav <n-yadav@ti.com> To: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org> CC: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v2 1/2] arm64: dts: ti: k3-am62a-main: Add sdhci0 instance Date: Mon, 30 Oct 2023 12:01:07 +0530 Message-ID: <20231030063108.1242981-2-n-yadav@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231030063108.1242981-1-n-yadav@ti.com> References: <20231030063108.1242981-1-n-yadav@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-1.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:32:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161040488460664 X-GMAIL-MSGID: 1781161040488460664 |
Series |
Add eMMC support for AM62a SK
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Commit Message
Nitin Yadav
Oct. 30, 2023, 6:31 a.m. UTC
Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
ITAP values as they are NA in datasheet[0] for lower speed modes.
[0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Comments
On 10/30/23 1:31 AM, Nitin Yadav wrote: > Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping > ITAP values as they are NA in datasheet[0] for lower speed modes. > > [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179) > Minor comment below. All else looks good to me. Reviewed by: Judith Mendez <jm@ti.com> > Signed-off-by: Nitin Yadav <n-yadav@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi > index de36abb243f1..89b8b7d302cd 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi > @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 { > status = "disabled"; > }; > > + sdhci0: mmc@fa10000 { > + compatible = "ti,am62-sdhci"; > + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; > + clock-names = "clk_ahb", "clk_xin"; > + assigned-clocks = <&k3_clks 57 6>; > + assigned-clock-parents = <&k3_clks 57 8>; > + mmc-hs200-1_8v; > + ti,trm-icp = <0x2>; > + ti,otap-del-sel-legacy = <0x0>; > + ti,otap-del-sel-mmc-hs = <0x0>; > + ti,otap-del-sel-hs200 = <0x6>; I am wondering why DDR52 speed mode was not added? > + bus-width = <8>; > + ti,clkbuf-sel = <0x7>; > + status = "disabled"; > + }; > + > sdhci1: mmc@fa00000 { > compatible = "ti,am62-sdhci"; > reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; ~ Judith
On 11/28/2023 3:11 AM, Judith Mendez wrote: > On 10/30/23 1:31 AM, Nitin Yadav wrote: >> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping >> ITAP values as they are NA in datasheet[0] for lower speed modes. >> >> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179) >> > > Minor comment below. All else looks good to me. > > Reviewed by: Judith Mendez <jm@ti.com> > >> Signed-off-by: Nitin Yadav <n-yadav@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> index de36abb243f1..89b8b7d302cd 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 { >> status = "disabled"; >> }; >> + sdhci0: mmc@fa10000 { >> + compatible = "ti,am62-sdhci"; >> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; >> + clock-names = "clk_ahb", "clk_xin"; >> + assigned-clocks = <&k3_clks 57 6>; >> + assigned-clock-parents = <&k3_clks 57 8>; >> + mmc-hs200-1_8v; >> + ti,trm-icp = <0x2>; >> + ti,otap-del-sel-legacy = <0x0>; >> + ti,otap-del-sel-mmc-hs = <0x0>; >> + ti,otap-del-sel-hs200 = <0x6>; > > I am wondering why DDR52 speed mode was not added? plz refer datasheet. No mention of DDR52 in this revised addition. > >> + bus-width = <8>; >> + ti,clkbuf-sel = <0x7>; >> + status = "disabled"; >> + }; >> + >> sdhci1: mmc@fa00000 { >> compatible = "ti,am62-sdhci"; >> reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; > > ~ Judith
Hi Nitin, On 11/27/23 10:39 PM, Nitin Yadav wrote: > > > On 11/28/2023 3:11 AM, Judith Mendez wrote: >> On 10/30/23 1:31 AM, Nitin Yadav wrote: >>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping >>> ITAP values as they are NA in datasheet[0] for lower speed modes. >>> >>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179) >>> >> >> Minor comment below. All else looks good to me. >> >> Reviewed by: Judith Mendez <jm@ti.com> >> >>> Signed-off-by: Nitin Yadav <n-yadav@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++ >>> 1 file changed, 19 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >>> index de36abb243f1..89b8b7d302cd 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi >>> @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 { >>> status = "disabled"; >>> }; >>> + sdhci0: mmc@fa10000 { >>> + compatible = "ti,am62-sdhci"; >>> + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; >>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >>> + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; >>> + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; >>> + clock-names = "clk_ahb", "clk_xin"; >>> + assigned-clocks = <&k3_clks 57 6>; >>> + assigned-clock-parents = <&k3_clks 57 8>; >>> + mmc-hs200-1_8v; >>> + ti,trm-icp = <0x2>; >>> + ti,otap-del-sel-legacy = <0x0>; >>> + ti,otap-del-sel-mmc-hs = <0x0>; >>> + ti,otap-del-sel-hs200 = <0x6>; >> >> I am wondering why DDR52 speed mode was not added? > plz refer datasheet. No mention of DDR52 in this revised addition. I believe it is mentioned in the RIOT, not datasheet. >> >>> + bus-width = <8>; >>> + ti,clkbuf-sel = <0x7>; >>> + status = "disabled"; >>> + }; >>> + >>> sdhci1: mmc@fa00000 { >>> compatible = "ti,am62-sdhci"; >>> reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; >> >> ~ Judith
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index de36abb243f1..89b8b7d302cd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -488,6 +488,25 @@ main_gpio1: gpio@601000 { status = "disabled"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + mmc-hs200-1_8v; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-hs200 = <0x6>; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + status = "disabled"; + }; + sdhci1: mmc@fa00000 { compatible = "ti,am62-sdhci"; reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;