diff mbox series

s390: Fix ICE in testcase pr89233

Message ID 20231115131252.25924-1-jchrist@linux.ibm.com
State Accepted
Headers
Series s390: Fix ICE in testcase pr89233 |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Juergen Christ Nov. 15, 2023, 1:12 p.m. UTC 
  When using GNU vector extensions, an access outside of the vector size
caused an ICE on s390.  Fix this by aligning with the vec_extract
builtin, i.e., computing constant index modulo number of lanes.

Fixes testcase gcc.target/s390/pr89233.c.

Bootstrapped and tested on s390.  OK for mainline?

gcc/ChangeLog:

	* config/s390/vector.md: (*vec_extract) Fix.

Signed-off-by: Juergen Christ <jchrist@linux.ibm.com>
---
 gcc/config/s390/vector.md | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Comments

Andreas Krebbel Nov. 23, 2023, 2:33 p.m. UTC | #1 
On 11/15/23 14:12, Juergen Christ wrote:
> When using GNU vector extensions, an access outside of the vector size
> caused an ICE on s390.  Fix this by aligning with the vec_extract
> builtin, i.e., computing constant index modulo number of lanes.
> 
> Fixes testcase gcc.target/s390/pr89233.c.
> 
> Bootstrapped and tested on s390.  OK for mainline?
> 
> gcc/ChangeLog:
> 
> 	* config/s390/vector.md: (*vec_extract) Fix.

Committed to mainline. Thanks!

Andreas
diff mbox series

Patch

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 7d1eb36e8446..deda5990a035 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -532,12 +532,14 @@ 
          (match_operand:V        1 "nonmemory_operand"  "v,v")
          (parallel
           [(match_operand:SI     2 "nonmemory_operand" "an,I")])))]
-  "TARGET_VX
-   && (!CONST_INT_P (operands[2])
-       || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))"
-  "@
-   vlgv<bhfgq>\t%0,%v1,%Y2
-   vste<bhfgq>\t%v1,%0,%2"
+  "TARGET_VX"
+  {
+    if (CONST_INT_P (operands[2]))
+	  operands[2] = GEN_INT (UINTVAL (operands[2]) & (GET_MODE_NUNITS (<V:MODE>mode) - 1));
+    if (which_alternative == 0)
+      return "vlgv<bhfgq>\t%0,%v1,%Y2";
+	return "vste<bhfgq>\t%v1,%0,%2";
+  }
   [(set_attr "op_type" "VRS,VRX")])
 
 ; vlgvb, vlgvh, vlgvf, vlgvg