Message ID | 20231117113931.26660-2-quic_sibis@quicinc.com |
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State | New |
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Fri, 17 Nov 2023 11:40:07 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHBe6WD004639 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:40:06 GMT Received: from blr-ubuntu-87.ap.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 17 Nov 2023 03:39:59 -0800 From: Sibi Sankar <quic_sibis@quicinc.com> To: <andersson@kernel.org>, <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <catalin.marinas@arm.com>, <ulf.hansson@linaro.org> CC: <agross@kernel.org>, <conor+dt@kernel.org>, <ayan.kumar.halder@amd.com>, <j@jannau.net>, <dmitry.baryshkov@linaro.org>, <nfraprado@collabora.com>, <m.szyprowski@samsung.com>, <u-kumar1@ti.com>, <peng.fan@nxp.com>, <lpieralisi@kernel.org>, <quic_rjendra@quicinc.com>, <abel.vesa@linaro.org>, <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <quic_tsoni@quicinc.com>, <neil.armstrong@linaro.org>, Sibi Sankar <quic_sibis@quicinc.com> Subject: [PATCH V2 1/5] dt-bindings: arm: cpus: Add qcom,oryon compatible Date: Fri, 17 Nov 2023 17:09:27 +0530 Message-ID: <20231117113931.26660-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231117113931.26660-1-quic_sibis@quicinc.com> References: <20231117113931.26660-1-quic_sibis@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: s80nqTBJnEBahMXAxwu36mvX3eUwVz8b X-Proofpoint-ORIG-GUID: s80nqTBJnEBahMXAxwu36mvX3eUwVz8b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_08,2023-11-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=956 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170087 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); 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Series |
dts: qcom: Introduce X1E80100 platforms device tree
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Commit Message
Sibi Sankar
Nov. 17, 2023, 11:39 a.m. UTC
From: Rajendra Nayak <quic_rjendra@quicinc.com> These are the CPU cores in Qualcomm's X1E80100 SoC. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- v2: * Update the part number from sc8380xp to x1e80100. Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Comments
On Fri, Nov 17, 2023 at 05:09:27PM +0530, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > These are the CPU cores in Qualcomm's X1E80100 SoC. > > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > > v2: > * Update the part number from sc8380xp to x1e80100. > > Documentation/devicetree/bindings/arm/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > index ffd526363fda..cc5a21b47e26 100644 > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > @@ -198,6 +198,7 @@ properties: > - qcom,kryo660 > - qcom,kryo685 > - qcom,kryo780 > + - qcom,oryon Wasn't it previously said 'oryon' is not specific enough? Also, please describe what oryon is in the commit msg. Rob
Hey Rob, Thanks for taking time to review the series. On 11/19/23 21:29, Rob Herring wrote: > On Fri, Nov 17, 2023 at 05:09:27PM +0530, Sibi Sankar wrote: >> From: Rajendra Nayak <quic_rjendra@quicinc.com> >> >> These are the CPU cores in Qualcomm's X1E80100 SoC. >> >> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- >> >> v2: >> * Update the part number from sc8380xp to x1e80100. >> >> Documentation/devicetree/bindings/arm/cpus.yaml | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml >> index ffd526363fda..cc5a21b47e26 100644 >> --- a/Documentation/devicetree/bindings/arm/cpus.yaml >> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml >> @@ -198,6 +198,7 @@ properties: >> - qcom,kryo660 >> - qcom,kryo685 >> - qcom,kryo780 >> + - qcom,oryon > > Wasn't it previously said 'oryon' is not specific enough? > > Also, please describe what oryon is in the commit msg. ack. Will add more details in the next re-spin. -Sibi > > Rob
On 11/20/23 12:14, Sibi Sankar wrote: > Hey Rob, > > Thanks for taking time to review the series. > > On 11/19/23 21:29, Rob Herring wrote: >> On Fri, Nov 17, 2023 at 05:09:27PM +0530, Sibi Sankar wrote: >>> From: Rajendra Nayak <quic_rjendra@quicinc.com> >>> >>> These are the CPU cores in Qualcomm's X1E80100 SoC. >>> >>> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> >>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >>> --- >>> >>> v2: >>> * Update the part number from sc8380xp to x1e80100. >>> >>> Documentation/devicetree/bindings/arm/cpus.yaml | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml >>> b/Documentation/devicetree/bindings/arm/cpus.yaml >>> index ffd526363fda..cc5a21b47e26 100644 >>> --- a/Documentation/devicetree/bindings/arm/cpus.yaml >>> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml >>> @@ -198,6 +198,7 @@ properties: >>> - qcom,kryo660 >>> - qcom,kryo685 >>> - qcom,kryo780 >>> + - qcom,oryon >> >> Wasn't it previously said 'oryon' is not specific enough? https://lore.kernel.org/lkml/b165d2cd-e8da-4f6d-9ecf-14df2b803614@linaro.org/ The cpu part numbers were indeed different in engineering samples which has now been fixed in the production version. -Sibi >> >> Also, please describe what oryon is in the commit msg. > > ack. Will add more details in the next re-spin. > > -Sibi > >> >> Rob
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index ffd526363fda..cc5a21b47e26 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -198,6 +198,7 @@ properties: - qcom,kryo660 - qcom,kryo685 - qcom,kryo780 + - qcom,oryon - qcom,scorpion enable-method: