diff mbox series

[RFC,3/5] arm64: dts: renesas: r9a07g043[u]: Add IRQC node

Message ID	20221107175305.63975-4-prabhakar.mahadev-lad.rj@bp.renesas.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Prabhakar <prabhakar.csengg@gmail.com> To: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [PATCH RFC 3/5] arm64: dts: renesas: r9a07g043[u]: Add IRQC node Date: Mon, 7 Nov 2022 17:53:03 +0000 Message-Id: <20221107175305.63975-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221107175305.63975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add IRQC support to RZ/G2UL SoC \| [RFC,0/5] Add IRQC support to RZ/G2UL SoC [RFC,1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC [RFC,2/5] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts [RFC,3/5] arm64: dts: renesas: r9a07g043[u]: Add IRQC node [RFC,4/5] arm64: dts: renesas: r9a07g043[u]: Update pinctrl node to handle GPIO interrupts [RFC,5/5] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}

Commit Message

Lad, Prabhakar Nov. 7, 2022, 5:53 p.m. UTC

  From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note,
- clocks and resets are differnt when compared to RZ/Five hence its added
  in r9a07g043u.dtsi
- We have additional interrupt on RZ/Five hence interrupts are added in
  r9a07g043u.dtsi
- clock-names is also added in r9a07g043u.dtsi to avoid dtbs_check warning
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi  |  8 ++++
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 50 +++++++++++++++++++++
 2 files changed, 58 insertions(+)

Comments

Geert Uytterhoeven Nov. 17, 2022, 11:13 a.m. UTC | #1

Hi Prabhakar,

On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> ---
> Note,
> - clocks and resets are differnt when compared to RZ/Five hence its added
>   in r9a07g043u.dtsi
> - We have additional interrupt on RZ/Five hence interrupts are added in
>   r9a07g043u.dtsi

Which additional interrupts?
Do you already have the r9a06g043f-variant ready, so we can compare?

> - clock-names is also added in r9a07g043u.dtsi to avoid dtbs_check warning

Why does this warn?

> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> @@ -538,6 +538,14 @@ pinctrl: pinctrl@11030000 {
>                                  <&cpg R9A07G043_GPIO_SPARE_RESETN>;
>                 };
>
> +               irqc: interrupt-controller@110a0000 {
> +                       #interrupt-cells = <2>;
> +                       #address-cells = <0>;
> +                       interrupt-controller;
> +                       reg = <0 0x110a0000 0 0x10000>;

The size of the "reg" property will be 0x20000 on RZ/Five, to cover the
extra [NIT]MSK registers, so I think this belongs in r9a07g043u.dtsi, too.

> +                       power-domains = <&cpg>;
> +               };
> +
>                 dmac: dma-controller@11820000 {
>                         compatible = "renesas,r9a07g043-dmac",
>                                      "renesas,rz-dmac";

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Lad, Prabhakar Nov. 17, 2022, 12:30 p.m. UTC | #2

Hi Geert,

Thank you for the review.

On Thu, Nov 17, 2022 at 11:13 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > ---
> > Note,
> > - clocks and resets are differnt when compared to RZ/Five hence its added
> >   in r9a07g043u.dtsi
> > - We have additional interrupt on RZ/Five hence interrupts are added in
> >   r9a07g043u.dtsi
>
> Which additional interrupts?
> Do you already have the r9a06g043f-variant ready, so we can compare?
>
I missed this RZ/G2UL has this interrupt too. So ignore this point.

> > - clock-names is also added in r9a07g043u.dtsi to avoid dtbs_check warning
>
> Why does this warn?
>
If we add the clock-names property in the base dtsi we get a
dtbs_check warning "clocks is a dependency of clock-names" for RZ/Five
as we haven't added the clocks property to it.

> > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > @@ -538,6 +538,14 @@ pinctrl: pinctrl@11030000 {
> >                                  <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> >                 };
> >
> > +               irqc: interrupt-controller@110a0000 {
> > +                       #interrupt-cells = <2>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       reg = <0 0x110a0000 0 0x10000>;
>
> The size of the "reg" property will be 0x20000 on RZ/Five, to cover the
> extra [NIT]MSK registers, so I think this belongs in r9a07g043u.dtsi, too.
>
Agreed.

Cheers,
Prabhakar

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 3f7d451b1199..44b9bc6294be 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -538,6 +538,14 @@  pinctrl: pinctrl@11030000 {
 				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
 		};
 
+		irqc: interrupt-controller@110a0000 {
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0 0x110a0000 0 0x10000>;
+			power-domains = <&cpg>;
+		};
+
 		dmac: dma-controller@11820000 {
 			compatible = "renesas,r9a07g043-dmac",
 				     "renesas,rz-dmac";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index b8bf06b51235..7a8ed7ae253b 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -48,6 +48,56 @@  timer {
 	};
 };
 
+&irqc {
+	compatible = "renesas,r9a07g043u-irqc",
+		     "renesas,rzg2l-irqc";
+	interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
+		     <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
+		 <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
+	clock-names = "clk", "pclk";
+	resets = <&cpg R9A07G043_IA55_RESETN>;
+};
+
 &soc {
 	interrupt-parent = <&gic>;