diff mbox series

[1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b

Message ID	20231113005702.2467-2-jszhang@kernel.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; From: Jisheng Zhang <jszhang@kernel.org> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>, Chen Wang <unicorn_wang@outlook.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b Date: Mon, 13 Nov 2023 08:57:01 +0800 Message-Id: <20231113005702.2467-2-jszhang@kernel.org> In-Reply-To: <20231113005702.2467-1-jszhang@kernel.org> References: <20231113005702.2467-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: sophgo: add pinctrl support for cv1800b \| [0/2] riscv: sophgo: add pinctrl support for cv1800b [1/2] riscv: dts: cv1800b: add pinctrl node for cv1800b [2/2] riscv: dts: sophgo: set pinctrl for uart0

Commit Message

Jisheng Zhang Nov. 13, 2023, 12:57 a.m. UTC

  Add the reset device tree node to cv1800b SoC reusing the
pinctrl-single driver.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h

Comments

Samuel Holland Nov. 13, 2023, 1:51 a.m. UTC | #1

On 2023-11-12 6:57 PM, Jisheng Zhang wrote:
> Add the reset device tree node to cv1800b SoC reusing the
          ^^^^^
          I assume you mean pinctrl here?

> pinctrl-single driver.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
>  2 files changed, 29 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> new file mode 100644
> index 000000000000..ed78b6fb3142
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h

A couple of questions: Should this go in include/dt-bindings? And is it worth
including macros for the actual function mappings, like in the vendor source[1]?

[1]:
https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/cv180x_pinlist_swconfig.h

> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> + *
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + */
> +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +
> +#define MUX_M0		0
> +#define MUX_M1		1
> +#define MUX_M2		2
> +#define MUX_M3		3
> +#define MUX_M4		4
> +#define MUX_M5		5
> +#define MUX_M6		6
> +#define MUX_M7		7
> +
> +#endif
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index e04df04a91c0..7a44d8e8672b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -6,6 +6,8 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
>  
> +#include "cv-pinctrl.h"
> +
>  / {
>  	compatible = "sophgo,cv1800b";
>  	#address-cells = <1>;
> @@ -55,6 +57,14 @@ soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		pinctrl0: pinctrl@3001000 {
> +			compatible = "pinctrl-single";
> +			reg = <0x3001000 0x130>;
> +			#pinctrl-cells = <1>;
> +			pinctrl-single,register-width = <32>;
> +			pinctrl-single,function-mask = <0x00000007>;
> +		};

From the vendor driver[2], it looks like this peripheral block only handles
pinmuxing, so indeed this looks like a good use of pinctrl-single.

[2]:
https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/pinctrl-cv180x.h

> +
>  		rst: reset-controller@3003000 {
>  			compatible = "sophgo,cv1800b-reset";
>  			reg = <0x03003000 0x1000>;

Jisheng Zhang Nov. 13, 2023, 1:03 p.m. UTC | #2

On Sun, Nov 12, 2023 at 08:51:20PM -0500, Samuel Holland wrote:
> On 2023-11-12 6:57 PM, Jisheng Zhang wrote:
> > Add the reset device tree node to cv1800b SoC reusing the
>           ^^^^^
>           I assume you mean pinctrl here?

oops copy and paste the commit msg ;) thanks
> 
> > pinctrl-single driver.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
> >  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
> >  2 files changed, 29 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > new file mode 100644
> > index 000000000000..ed78b6fb3142
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> 
> A couple of questions: Should this go in include/dt-bindings? And is it worth

When I cooked this series two weeks ago, I did put it in dt-binding, but
then I found commit fe49f2d776f799 ("arm64: dts: ti: Use local header for
pinctrl register values"), "These definitions were previously put in the
bindings header to avoid code duplication and to provide some context
meaning (name), but they do not fit the purpose of bindings." which is
suggested and acked by Krzysztof, so I just want to follow the style
here.


> including macros for the actual function mappings, like in the vendor source[1]?

Do you want something as the following?

#define UART0_TX	0
#define CAM_MCLK1	1
...

#define REG_UART0_TX	0x24
...

pinctrl-single,pins = <REG_UART0_TX UART0_TX>;

Other pinctl-single users just uses the register value directly, I have
no preference. But I'd like to get suggestions from DT and pinctl-single
maintainers. Hi Rob, Krzysztof, Conor, Tony, what's your opinion?

> 
> [1]:
> https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/cv180x_pinlist_swconfig.h
> 
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> > + *
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > +
> > +#define MUX_M0		0
> > +#define MUX_M1		1
> > +#define MUX_M2		2
> > +#define MUX_M3		3
> > +#define MUX_M4		4
> > +#define MUX_M5		5
> > +#define MUX_M6		6
> > +#define MUX_M7		7
> > +
> > +#endif
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index e04df04a91c0..7a44d8e8672b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -6,6 +6,8 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
> >  
> > +#include "cv-pinctrl.h"
> > +
> >  / {
> >  	compatible = "sophgo,cv1800b";
> >  	#address-cells = <1>;
> > @@ -55,6 +57,14 @@ soc {
> >  		dma-noncoherent;
> >  		ranges;
> >  
> > +		pinctrl0: pinctrl@3001000 {
> > +			compatible = "pinctrl-single";
> > +			reg = <0x3001000 0x130>;
> > +			#pinctrl-cells = <1>;
> > +			pinctrl-single,register-width = <32>;
> > +			pinctrl-single,function-mask = <0x00000007>;
> > +		};
> 
> From the vendor driver[2], it looks like this peripheral block only handles
> pinmuxing, so indeed this looks like a good use of pinctrl-single.

This is deffinitely pinctrl-single style pinmux controller ;)

> 
> [2]:
> https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/pinctrl-cv180x.h
> 
> > +
> >  		rst: reset-controller@3003000 {
> >  			compatible = "sophgo,cv1800b-reset";
> >  			reg = <0x03003000 0x1000>;
>

Conor Dooley Nov. 13, 2023, 1:29 p.m. UTC | #3

On Mon, Nov 13, 2023 at 09:03:11PM +0800, Jisheng Zhang wrote:
> On Sun, Nov 12, 2023 at 08:51:20PM -0500, Samuel Holland wrote:
> > On 2023-11-12 6:57 PM, Jisheng Zhang wrote:
> > > Add the reset device tree node to cv1800b SoC reusing the
> >           ^^^^^
> >           I assume you mean pinctrl here?
> 
> oops copy and paste the commit msg ;) thanks
> > 
> > > pinctrl-single driver.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
> > >  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
> > >  2 files changed, 29 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > > 
> > > diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > > new file mode 100644
> > > index 000000000000..ed78b6fb3142
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > 
> > A couple of questions: Should this go in include/dt-bindings? And is it worth
> 
> When I cooked this series two weeks ago, I did put it in dt-binding, but
> then I found commit fe49f2d776f799 ("arm64: dts: ti: Use local header for
> pinctrl register values"), "These definitions were previously put in the
> bindings header to avoid code duplication and to provide some context
> meaning (name), but they do not fit the purpose of bindings." which is
> suggested and acked by Krzysztof, so I just want to follow the style
> here.
> 
> 
> > including macros for the actual function mappings, like in the vendor source[1]?
> 
> Do you want something as the following?
> 
> #define UART0_TX	0
> #define CAM_MCLK1	1
> ...
> 
> #define REG_UART0_TX	0x24
> ...
> 
> pinctrl-single,pins = <REG_UART0_TX UART0_TX>;
> 
> Other pinctl-single users just uses the register value directly, I have
> no preference. But I'd like to get suggestions from DT and pinctl-single
> maintainers. Hi Rob, Krzysztof, Conor, Tony, what's your opinion?

Basically, if the definitions map directly to registers and are just
used to make writing your devicetree easier then they do not belong
in a binding. This differs from clock or reset indices, where we
essentially make up a set of indices that may or may not correlate to
offsets in the hardware as using the register values without any sort of
abstraction is not defining an ABI.

Cheers,
Conor.
> 
> > 
> > [1]:
> > https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/cv180x_pinlist_swconfig.h
> > 
> > > @@ -0,0 +1,19 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> > > + *
> > > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > > + */
> > > +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > > +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > > +
> > > +#define MUX_M0		0
> > > +#define MUX_M1		1
> > > +#define MUX_M2		2
> > > +#define MUX_M3		3
> > > +#define MUX_M4		4
> > > +#define MUX_M5		5
> > > +#define MUX_M6		6
> > > +#define MUX_M7		7
> > > +
> > > +#endif
> > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > index e04df04a91c0..7a44d8e8672b 100644
> > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > > @@ -6,6 +6,8 @@
> > >  #include <dt-bindings/interrupt-controller/irq.h>
> > >  #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
> > >  
> > > +#include "cv-pinctrl.h"
> > > +
> > >  / {
> > >  	compatible = "sophgo,cv1800b";
> > >  	#address-cells = <1>;
> > > @@ -55,6 +57,14 @@ soc {
> > >  		dma-noncoherent;
> > >  		ranges;
> > >  
> > > +		pinctrl0: pinctrl@3001000 {
> > > +			compatible = "pinctrl-single";
> > > +			reg = <0x3001000 0x130>;
> > > +			#pinctrl-cells = <1>;
> > > +			pinctrl-single,register-width = <32>;
> > > +			pinctrl-single,function-mask = <0x00000007>;
> > > +		};
> > 
> > From the vendor driver[2], it looks like this peripheral block only handles
> > pinmuxing, so indeed this looks like a good use of pinctrl-single.
> 
> This is deffinitely pinctrl-single style pinmux controller ;)
> 
> > 
> > [2]:
> > https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/pinctrl/cvitek/pinctrl-cv180x.h
> > 
> > > +
> > >  		rst: reset-controller@3003000 {
> > >  			compatible = "sophgo,cv1800b-reset";
> > >  			reg = <0x03003000 0x1000>;
> >

Samuel Holland Nov. 13, 2023, 1:49 p.m. UTC | #4

Hi Conor,

On 2023-11-13 7:29 AM, Conor Dooley wrote:
> On Mon, Nov 13, 2023 at 09:03:11PM +0800, Jisheng Zhang wrote:
>> On Sun, Nov 12, 2023 at 08:51:20PM -0500, Samuel Holland wrote:
>>> On 2023-11-12 6:57 PM, Jisheng Zhang wrote:
>>>> Add the reset device tree node to cv1800b SoC reusing the
>>>           ^^^^^
>>>           I assume you mean pinctrl here?
>>
>> oops copy and paste the commit msg ;) thanks
>>>
>>>> pinctrl-single driver.
>>>>
>>>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>>>> ---
>>>>  arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
>>>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
>>>>  2 files changed, 29 insertions(+)
>>>>  create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
>>>>
>>>> diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
>>>> new file mode 100644
>>>> index 000000000000..ed78b6fb3142
>>>> --- /dev/null
>>>> +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
>>>
>>> A couple of questions: Should this go in include/dt-bindings? And is it worth
>>
>> When I cooked this series two weeks ago, I did put it in dt-binding, but
>> then I found commit fe49f2d776f799 ("arm64: dts: ti: Use local header for
>> pinctrl register values"), "These definitions were previously put in the
>> bindings header to avoid code duplication and to provide some context
>> meaning (name), but they do not fit the purpose of bindings." which is
>> suggested and acked by Krzysztof, so I just want to follow the style
>> here.
>>
>>
>>> including macros for the actual function mappings, like in the vendor source[1]?
>>
>> Do you want something as the following?
>>
>> #define UART0_TX	0
>> #define CAM_MCLK1	1
>> ...
>>
>> #define REG_UART0_TX	0x24
>> ...
>>
>> pinctrl-single,pins = <REG_UART0_TX UART0_TX>;
>>
>> Other pinctl-single users just uses the register value directly, I have
>> no preference. But I'd like to get suggestions from DT and pinctl-single
>> maintainers. Hi Rob, Krzysztof, Conor, Tony, what's your opinion?
> 
> Basically, if the definitions map directly to registers and are just
> used to make writing your devicetree easier then they do not belong
> in a binding. This differs from clock or reset indices, where we
> essentially make up a set of indices that may or may not correlate to
> offsets in the hardware as using the register values without any sort of
> abstraction is not defining an ABI.

Right. I should have remembered this policy :)

Regards,
Samuel

Chen Wang Nov. 14, 2023, 1:38 a.m. UTC | #5

On 2023/11/13 8:57, Jisheng Zhang wrote:
> Add the reset device tree node to cv1800b SoC reusing the
> pinctrl-single driver.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>   arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
>   2 files changed, 29 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h


I'm afraid there will not be more cv* chip in coming days. So I would 
suggest you use "cv1800b-pinctrl.h" first here. If we see more cv* 
coming, and if they will reuse the definition here, we can consider 
optimize the filename, what do you think?

BTW, how about defining the file name as "cv1800b.h" and I'm not sure if 
you will have more macro const definition for other modules?

> diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> new file mode 100644
> index 000000000000..ed78b6fb3142
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> + *
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + */
> +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +
> +#define MUX_M0		0
> +#define MUX_M1		1
> +#define MUX_M2		2
> +#define MUX_M3		3
> +#define MUX_M4		4
> +#define MUX_M5		5
> +#define MUX_M6		6
> +#define MUX_M7		7
> +
> +#endif
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index e04df04a91c0..7a44d8e8672b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -6,6 +6,8 @@
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
>   
> +#include "cv-pinctrl.h"
> +
>   / {
>   	compatible = "sophgo,cv1800b";
>   	#address-cells = <1>;
> @@ -55,6 +57,14 @@ soc {
>   		dma-noncoherent;
>   		ranges;
>   
> +		pinctrl0: pinctrl@3001000 {
> +			compatible = "pinctrl-single";
> +			reg = <0x3001000 0x130>;
> +			#pinctrl-cells = <1>;
> +			pinctrl-single,register-width = <32>;
> +			pinctrl-single,function-mask = <0x00000007>;
> +		};
> +
>   		rst: reset-controller@3003000 {
>   			compatible = "sophgo,cv1800b-reset";
>   			reg = <0x03003000 0x1000>;

Chen Wang Nov. 14, 2023, 2:07 a.m. UTC | #6

On 2023/11/13 8:57, Jisheng Zhang wrote:
> Add the reset device tree node to cv1800b SoC reusing the
> pinctrl-single driver.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>   arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
>   2 files changed, 29 insertions(+)
>   create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> new file mode 100644
> index 000000000000..ed78b6fb3142
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> + *
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + */
> +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +
> +#define MUX_M0		0
> +#define MUX_M1		1
> +#define MUX_M2		2
> +#define MUX_M3		3
> +#define MUX_M4		4
> +#define MUX_M5		5
> +#define MUX_M6		6
> +#define MUX_M7		7
> +
> +#endif
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index e04df04a91c0..7a44d8e8672b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -6,6 +6,8 @@
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/reset/sophgo,cv1800b-reset.h>

Another question:

Does this patch depend on anther patchset "riscv: sophgo: add reset 
support for cv1800b"?

If so, you may need to add comments in the cover-letter to clarify this. 
But I'm afraid it does not.


>   
> +#include "cv-pinctrl.h"
> +
>   / {
>   	compatible = "sophgo,cv1800b";
>   	#address-cells = <1>;
> @@ -55,6 +57,14 @@ soc {
>   		dma-noncoherent;
>   		ranges;
>   
> +		pinctrl0: pinctrl@3001000 {
> +			compatible = "pinctrl-single";
> +			reg = <0x3001000 0x130>;
> +			#pinctrl-cells = <1>;
> +			pinctrl-single,register-width = <32>;
> +			pinctrl-single,function-mask = <0x00000007>;
> +		};
> +
>   		rst: reset-controller@3003000 {
>   			compatible = "sophgo,cv1800b-reset";
>   			reg = <0x03003000 0x1000>;

Jisheng Zhang Nov. 14, 2023, 2:46 p.m. UTC | #7

On Tue, Nov 14, 2023 at 09:38:47AM +0800, Chen Wang wrote:
> 
> On 2023/11/13 8:57, Jisheng Zhang wrote:
> > Add the reset device tree node to cv1800b SoC reusing the
> > pinctrl-single driver.
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >   arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
> >   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
> >   2 files changed, 29 insertions(+)
> >   create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> 
> 
> I'm afraid there will not be more cv* chip in coming days. So I would
> suggest you use "cv1800b-pinctrl.h" first here. If we see more cv* coming,
> and if they will reuse the definition here, we can consider optimize the
> filename, what do you think?
> 
> BTW, how about defining the file name as "cv1800b.h" and I'm not sure if you

hmm, cv1800b-pinctrl.h is fine. Only pinctrl related stuff will be put
there.

> will have more macro const definition for other modules?
> 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > new file mode 100644
> > index 000000000000..ed78b6fb3142
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> > + *
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> > +
> > +#define MUX_M0		0
> > +#define MUX_M1		1
> > +#define MUX_M2		2
> > +#define MUX_M3		3
> > +#define MUX_M4		4
> > +#define MUX_M5		5
> > +#define MUX_M6		6
> > +#define MUX_M7		7
> > +
> > +#endif
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index e04df04a91c0..7a44d8e8672b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -6,6 +6,8 @@
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
> > +#include "cv-pinctrl.h"
> > +
> >   / {
> >   	compatible = "sophgo,cv1800b";
> >   	#address-cells = <1>;
> > @@ -55,6 +57,14 @@ soc {
> >   		dma-noncoherent;
> >   		ranges;
> > +		pinctrl0: pinctrl@3001000 {
> > +			compatible = "pinctrl-single";
> > +			reg = <0x3001000 0x130>;
> > +			#pinctrl-cells = <1>;
> > +			pinctrl-single,register-width = <32>;
> > +			pinctrl-single,function-mask = <0x00000007>;
> > +		};
> > +
> >   		rst: reset-controller@3003000 {
> >   			compatible = "sophgo,cv1800b-reset";
> >   			reg = <0x03003000 0x1000>;

Rob Herring Nov. 16, 2023, 4:36 p.m. UTC | #8

On Mon, Nov 13, 2023 at 08:57:01AM +0800, Jisheng Zhang wrote:
> Add the reset device tree node to cv1800b SoC reusing the
> pinctrl-single driver.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/boot/dts/sophgo/cv-pinctrl.h | 19 +++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++++++++
>  2 files changed, 29 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> new file mode 100644
> index 000000000000..ed78b6fb3142
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Please match the licensing of the file(s) that include this. Not that 
there really anything 

> +/*
> + * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
> + *
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + */
> +#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
> +
> +#define MUX_M0		0
> +#define MUX_M1		1
> +#define MUX_M2		2
> +#define MUX_M3		3
> +#define MUX_M4		4
> +#define MUX_M5		5
> +#define MUX_M6		6
> +#define MUX_M7		7

I find defines with the number in the name to be somewhat pointless.

> +
> +#endif
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index e04df04a91c0..7a44d8e8672b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -6,6 +6,8 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
>  
> +#include "cv-pinctrl.h"
> +
>  / {
>  	compatible = "sophgo,cv1800b";
>  	#address-cells = <1>;
> @@ -55,6 +57,14 @@ soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		pinctrl0: pinctrl@3001000 {
> +			compatible = "pinctrl-single";
> +			reg = <0x3001000 0x130>;
> +			#pinctrl-cells = <1>;
> +			pinctrl-single,register-width = <32>;
> +			pinctrl-single,function-mask = <0x00000007>;
> +		};

Even more pointless is the defines are not even used.

> +
>  		rst: reset-controller@3003000 {
>  			compatible = "sophgo,cv1800b-reset";
>  			reg = <0x03003000 0x1000>;
> -- 
> 2.42.0
>

diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv-pinctrl.h b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
new file mode 100644
index 000000000000..ed78b6fb3142
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv-pinctrl.h
@@ -0,0 +1,19 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for pinctrl bindings for Sophgo CV* SoC.
+ *
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+#ifndef _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+#define _DTS_RISCV_SOPHGO_CV_PINCTRL_H
+
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+#endif
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index e04df04a91c0..7a44d8e8672b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -6,6 +6,8 @@ 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/reset/sophgo,cv1800b-reset.h>
 
+#include "cv-pinctrl.h"
+
 / {
 	compatible = "sophgo,cv1800b";
 	#address-cells = <1>;
@@ -55,6 +57,14 @@  soc {
 		dma-noncoherent;
 		ranges;
 
+		pinctrl0: pinctrl@3001000 {
+			compatible = "pinctrl-single";
+			reg = <0x3001000 0x130>;
+			#pinctrl-cells = <1>;
+			pinctrl-single,register-width = <32>;
+			pinctrl-single,function-mask = <0x00000007>;
+		};
+
 		rst: reset-controller@3003000 {
 			compatible = "sophgo,cv1800b-reset";
 			reg = <0x03003000 0x1000>;