diff mbox series

riscv: dts: sophgo: remove address-cells from CV1800B intc node

Message ID IA1PR20MB49532613F5B4BD9753A1BB4DBBB3A@IA1PR20MB4953.namprd20.prod.outlook.com
State New
Headers
Series riscv: dts: sophgo: remove address-cells from CV1800B intc node |

Commit Message

Inochi Amaoto Nov. 13, 2023, 9:26 a.m. UTC 
  A recent submission from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus. But CV1800B does
not follow this change and still uses #address-cells in its interrupt
controller. As it has no child nodes, #address-cells is not needed and
can be removed.

Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
 1 file changed, 1 deletion(-)

--
2.42.1

Comments

Conor Dooley Nov. 13, 2023, 1:14 p.m. UTC | #1 
On Mon, Nov 13, 2023 at 05:26:15PM +0800, Inochi Amaoto wrote:
> A recent submission from Rob has added additionalProperties: false
> to the interrupt-controller child node of RISC-V cpus. But CV1800B does
> not follow this change and still uses #address-cells in its interrupt
> controller. As it has no child nodes, #address-cells is not needed and
> can be removed.
> 
> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/

This is a dupe of a patch I already applied, but have not yet sent a PR
for:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/commit/?h=riscv-dt-for-next&id=b99df62818919b84e970eea5aec60b0dbc57da18

Cheers,
Conor.

> 
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..aec6401a467b 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
>  			cpu0_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
>  				interrupt-controller;
> -				#address-cells = <0>;
>  				#interrupt-cells = <1>;
>  			};
>  		};
> --
> 2.42.1
>
Inochi Amaoto Nov. 14, 2023, 12:41 a.m. UTC | #2 
>On Mon, Nov 13, 2023 at 05:26:15PM +0800, Inochi Amaoto wrote:
>> A recent submission from Rob has added additionalProperties: false
>> to the interrupt-controller child node of RISC-V cpus. But CV1800B does
>> not follow this change and still uses #address-cells in its interrupt
>> controller. As it has no child nodes, #address-cells is not needed and
>> can be removed.
>>
>> Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
>> Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/
>
>This is a dupe of a patch I already applied, but have not yet sent a PR

OK, I will try to check the tree next time.

>for:
>https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/commit/?h=riscv-dt-for-next&id=b99df62818919b84e970eea5aec60b0dbc57da18
>

Thanks.

>Cheers,
>Conor.
>
>>
>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
>>  1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> index df40e87ee063..aec6401a467b 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>> @@ -34,7 +34,6 @@ cpu0: cpu@0 {
>>  			cpu0_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>>  				interrupt-controller;
>> -				#address-cells = <0>;
>>  				#interrupt-cells = <1>;
>>  			};
>>  		};
>> --
>> 2.42.1
>>
>
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..aec6401a467b 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -34,7 +34,6 @@  cpu0: cpu@0 {
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
 				interrupt-controller;
-				#address-cells = <0>;
 				#interrupt-cells = <1>;
 			};
 		};