Message ID | 20230912072232.2455-1-jszhang@kernel.org |
---|---|
State | New |
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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id h2-20020a635302000000b00565ec2df68bsi4341404pgb.444.2023.09.12.00.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 00:41:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=B36S8DTT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 3DC9B8037A88; Tue, 12 Sep 2023 00:34:43 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231638AbjILHed (ORCPT <rfc822;pwkd43@gmail.com> + 39 others); Tue, 12 Sep 2023 03:34:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbjILHec (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 12 Sep 2023 03:34:32 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88B84B9; Tue, 12 Sep 2023 00:34:28 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A6DE0C433C8; Tue, 12 Sep 2023 07:34:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694504068; bh=xC6q3HYiwW9CEGzJvj/sjpQyCTVoGfRxTt9DU15lsZM=; h=From:To:Cc:Subject:Date:From; b=B36S8DTT292C3Y/z3w0PZdqkISNsor2tvJRyDzHkyvoejCDbdPUO+eAs2CVWuy3Ni HkDmMaRwCxbfPegnuc7asX99szOYHD/gq/kH9BcwqE5POyG1S0U+QCp4bvbC61Dleg zzdvafPvBPod5m5Yqgdb6ZRgtEr8ySKIhNnbIQYjceYnfIZWQueqxgs0Gc4oqFIjgn IQkacC0hQf0mCsutjBAROzg2nv9GRxjqgCyNTo2AUK+CFzV7H2L13Yvbzq4oI8flJE I8VnE/BeSrM3RcnwLyOuUh0E9ecDT66E71MzgOqRFIwkBKxBxAiA/4tS5LD1mwXfXT yWSKvvGQhV6Lg== From: Jisheng Zhang <jszhang@kernel.org> To: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini <dfustini@baylibre.com> Subject: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus Date: Tue, 12 Sep 2023 15:22:32 +0800 Message-Id: <20230912072232.2455-1-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 12 Sep 2023 00:34:43 -0700 (PDT) X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776816715972047122 X-GMAIL-MSGID: 1776816715972047122 |
Series |
[v2] riscv: dts: thead: set dma-noncoherent to soc bus
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Commit Message
Jisheng Zhang
Sept. 12, 2023, 7:22 a.m. UTC
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't dma coherent, so set dma-noncoherent to reflect this fact. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Tested-by: Drew Fustini <dfustini@baylibre.com> --- Since v1: - rebase on v6.6-rc1 - collect Tested-by tag arch/riscv/boot/dts/thead/th1520.dtsi | 1 + 1 file changed, 1 insertion(+)
Comments
On Tue, Sep 12, 2023 at 3:34 PM Jisheng Zhang <jszhang@kernel.org> wrote: > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > dma coherent, so set dma-noncoherent to reflect this fact. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Tested-by: Drew Fustini <dfustini@baylibre.com> > --- > > Since v1: > - rebase on v6.6-rc1 > - collect Tested-by tag > > arch/riscv/boot/dts/thead/th1520.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index ce708183b6f6..ff364709a6df 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -139,6 +139,7 @@ soc { > interrupt-parent = <&plic>; > #address-cells = <2>; > #size-cells = <2>; > + dma-noncoherent; Reviewed-by: Guo Ren <guoren@kernel.org> > ranges; > > plic: interrupt-controller@ffd8000000 { > -- > 2.40.1 >
On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > dma coherent, so set dma-noncoherent to reflect this fact. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Tested-by: Drew Fustini <dfustini@baylibre.com> > --- > > Since v1: > - rebase on v6.6-rc1 > - collect Tested-by tag Does this mean you're expecting me to take this? > > arch/riscv/boot/dts/thead/th1520.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > index ce708183b6f6..ff364709a6df 100644 > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > @@ -139,6 +139,7 @@ soc { > interrupt-parent = <&plic>; > #address-cells = <2>; > #size-cells = <2>; > + dma-noncoherent; > ranges; > > plic: interrupt-controller@ffd8000000 { > -- > 2.40.1 >
On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > --- > > > > Since v1: > > - rebase on v6.6-rc1 > > - collect Tested-by tag > > Does this mean you're expecting me to take this? Hi Conor, I think I will take this and send PR to soc people. The reason I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv mailist due to typo; Thank you so much > > > > > arch/riscv/boot/dts/thead/th1520.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi > > index ce708183b6f6..ff364709a6df 100644 > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi > > @@ -139,6 +139,7 @@ soc { > > interrupt-parent = <&plic>; > > #address-cells = <2>; > > #size-cells = <2>; > > + dma-noncoherent; > > ranges; > > > > plic: interrupt-controller@ffd8000000 { > > -- > > 2.40.1 > >
On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote: > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > > --- > > > > > > Since v1: > > > - rebase on v6.6-rc1 > > > - collect Tested-by tag > > > > Does this mean you're expecting me to take this? > > Hi Conor, > > I think I will take this and send PR to soc people. The reason > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv > mailist due to typo; Great, thanks. Please ask SFR to add your tree to linux-next. Cheers, Conor.
Hey Jisheng, On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote: > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote: > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > > > --- > > > > > > > > Since v1: > > > > - rebase on v6.6-rc1 > > > > - collect Tested-by tag > > > > > > Does this mean you're expecting me to take this? > > > > Hi Conor, > > > > I think I will take this and send PR to soc people. The reason > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv > > mailist due to typo; > > Great, thanks. Please ask SFR to add your tree to linux-next. I lost my main x86 box over the weekend (looks like probably a dead motherboard), so I may have missed a response to this. Did you see this email? Additionally, can you add that git tree to the maintainers entry for the thead devicetrees? Thanks, Conor.
On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote: > Hey Jisheng, > > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote: > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote: > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > > > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > > > > --- > > > > > > > > > > Since v1: > > > > > - rebase on v6.6-rc1 > > > > > - collect Tested-by tag > > > > > > > > Does this mean you're expecting me to take this? > > > > > > Hi Conor, > > > > > > I think I will take this and send PR to soc people. The reason > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv > > > mailist due to typo; > > > > Great, thanks. Please ask SFR to add your tree to linux-next. Hi Conor, I'm not sure how to do this. When MAINTAINERS patch is merged, send an email to Stephen Rothwell, are these steps correct? > > I lost my main x86 box over the weekend (looks like probably a dead > motherboard), so I may have missed a response to this. > > Did you see this email? Additionally, can you add that git tree to the > maintainers entry for the thead devicetrees? I just created a tree in git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git But it needs time for cgit to take place. I will send a patch once it appears. Thanks
On Thu, Sep 21, 2023 at 05:24:57PM +0800, Jisheng Zhang wrote: > On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote: > > Hey Jisheng, > > > > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote: > > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote: > > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > > > > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > > > > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > > > > > --- > > > > > > > > > > > > Since v1: > > > > > > - rebase on v6.6-rc1 > > > > > > - collect Tested-by tag > > > > > > > > > > Does this mean you're expecting me to take this? > > > > > > > > Hi Conor, > > > > > > > > I think I will take this and send PR to soc people. The reason > > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv > > > > mailist due to typo; > > > > > > Great, thanks. Please ask SFR to add your tree to linux-next. > > Hi Conor, > > I'm not sure how to do this. When MAINTAINERS patch is merged, send > an email to Stephen Rothwell, are these steps correct? Sorta, yeah. You don't need to have the MAINTAINERS patch merged first though, just send him a link to your tree and the branch name(s) & he will include it in linux-next. > > I lost my main x86 box over the weekend (looks like probably a dead > > motherboard), so I may have missed a response to this. > > > > Did you see this email? Additionally, can you add that git tree to the > > maintainers entry for the thead devicetrees? > > I just created a tree in > git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git > > But it needs time for cgit to take place. I will send a patch > once it appears. Looks to be there for me now. Thanks for doing this!
On Thu, Sep 21, 2023 at 11:08:28AM +0100, Conor Dooley wrote: > On Thu, Sep 21, 2023 at 05:24:57PM +0800, Jisheng Zhang wrote: > > On Wed, Sep 20, 2023 at 09:36:19AM +0100, Conor Dooley wrote: > > > Hey Jisheng, > > > > > > On Wed, Sep 13, 2023 at 04:44:18PM +0100, Conor Dooley wrote: > > > > On Wed, Sep 13, 2023 at 11:15:57PM +0800, Jisheng Zhang wrote: > > > > > On Tue, Sep 12, 2023 at 05:27:31PM +0100, Conor Dooley wrote: > > > > > > On Tue, Sep 12, 2023 at 03:22:32PM +0800, Jisheng Zhang wrote: > > > > > > > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > > > > > > > dma coherent, so set dma-noncoherent to reflect this fact. > > > > > > > > > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > > > > > Tested-by: Drew Fustini <dfustini@baylibre.com> > > > > > > > --- > > > > > > > > > > > > > > Since v1: > > > > > > > - rebase on v6.6-rc1 > > > > > > > - collect Tested-by tag > > > > > > > > > > > > Does this mean you're expecting me to take this? > > > > > > > > > > Hi Conor, > > > > > > > > > > I think I will take this and send PR to soc people. The reason > > > > > I send v2 is the rebasing on new rc1 and v1 wasn't in linux-riscv > > > > > mailist due to typo; > > > > > > > > Great, thanks. Please ask SFR to add your tree to linux-next. > > > > Hi Conor, > > > > I'm not sure how to do this. When MAINTAINERS patch is merged, send > > an email to Stephen Rothwell, are these steps correct? > > Sorta, yeah. You don't need to have the MAINTAINERS patch merged first > though, just send him a link to your tree and the branch name(s) & he > will include it in linux-next. > > > > I lost my main x86 box over the weekend (looks like probably a dead > > > motherboard), so I may have missed a response to this. > > > > > > Did you see this email? Additionally, can you add that git tree to the > > > maintainers entry for the thead devicetrees? > > > > I just created a tree in > > git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux.git > > > > But it needs time for cgit to take place. I will send a patch > > once it appears. > > Looks to be there for me now. Thanks for doing this! Hi Jisheng, I'm writing the cover letter for v2 of my th1520 mmc series and I am wondering if this dma-noncoherent patch is in any tree yet? Thanks, Drew
On Tue, Oct 17, 2023, at 18:09, Jisheng Zhang wrote: > On Mon, Oct 16, 2023 at 10:10:33AM -0700, Drew Fustini wrote: >> On Thu, Sep 21, 2023 at 11:08:28AM +0100, Conor Dooley wrote: >> >> Hi Jisheng, I'm writing the cover letter for v2 of my th1520 mmc series >> and I am wondering if this dma-noncoherent patch is in any tree yet? > > Hi Drew, > > I forget this patch. Thanks for reminding. > > Hi Arnd > > This is the only one dt fix for thead SoC, can you please pick it up > for the upcoming -rcN? I knew soc people can directly ask for pick > up for only one fix in the past. Let me know if I need to generate a > formal PR. Applied to the fixes branch now, thanks. There is no need for a pull request if you have just a single patch. Just a few things to consider: - For both patches and pull requests, make sure you have soc@kernel.org as the primary recipient so I know that I'm the one to apply them and see them in https://patchwork.kernel.org/project/linux-soc/list/ I get Cc'd on a lot of patches and would otherwise not know if you are looking for them to be applied or reviewed. - Since there is no tag description, add a comment under the '---' line asking for the patch to be applied directly, and say if this is a bugfix for the current release or if it should be queued for the next release. Arnd
Hello: This patch was applied to riscv/linux.git (fixes) by Arnd Bergmann <arnd@arndb.de>: On Tue, 12 Sep 2023 15:22:32 +0800 you wrote: > riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't > dma coherent, so set dma-noncoherent to reflect this fact. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Tested-by: Drew Fustini <dfustini@baylibre.com> > --- > > [...] Here is the summary with links: - [v2] riscv: dts: thead: set dma-noncoherent to soc bus https://git.kernel.org/riscv/c/759426c758c7 You are awesome, thank you!
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..ff364709a6df 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -139,6 +139,7 @@ soc { interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; + dma-noncoherent; ranges; plic: interrupt-controller@ffd8000000 {