diff mbox series

[v2,1/2] RISC-V: Add spill sp adjust check testcase.

Message ID 20221115083358.4130952-2-jiawei@iscas.ac.cn
State Accepted
Headers
Series RISC-V: Optimize RVV epilogue logic. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Jiawei Nov. 15, 2022, 8:33 a.m. UTC 
  This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

---
 .../gcc.target/riscv/rvv/base/spill-sp-adjust.c     | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

Comments

Jeff Law Nov. 17, 2022, 4:02 a.m. UTC | #1 
On 11/15/22 01:33, jiawei wrote:
> This testcase mix exist spill-1.c and adding new fun to check if
> there have redundant addi intructions. Idea provided by Jeff Law.
>
> gcc/testsuite/ChangeLog:
>
>          * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

I made several whitespace/formatting fixes to the riscv.cc part of this 
series, improved the Changelog and and committed it for you.


Thanks,

Jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 00000000000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)v; 
+}
+
+/* Make sure we do not have a useless SP adjustment.  */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */