@@ -668,7 +668,6 @@
; 32 bit int<->fp conversion instructions are available since VXE2 (z15).
(define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")])
-(define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")])
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
@@ -838,7 +837,7 @@
;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
;; and "cfdbr" in SImode.
-(define_mode_attr gf [(DI "g") (SI "f")])
+(define_mode_attr gf [(DI "g") (SI "f") (DF "g") (SF "f")])
;; In GPR templates, a string like sll<gk> will expand to sllg for DI
;; and sllk for SI. This way it is possible to merge the new z196 SI
@@ -897,6 +896,10 @@
(define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
+; Analogue to TOINTVEC / tointvec
+(define_mode_attr TOINT [(TF "TI") (DF "DI") (SF "SI")])
+(define_mode_attr toint [(TF "ti") (DF "di") (SF "si")])
+
;; Subst pattern definitions
(include "subst.md")
@@ -5266,16 +5269,15 @@
; df -> unsigned di, vxe2: sf -> unsigned si
; clgdbr, clfebr, wclgdb, wclfeb
-(define_insn "*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13"
- [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v")
- (unsigned_fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v")))
- (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
+(define_insn "*fixuns_trunc<mode><toint>2_z13"
+ [(set (match_operand:<TOINT> 0 "register_operand" "=d,v")
+ (unsigned_fix:<TOINT> (match_operand:VX_CONV_BFP 1 "register_operand" "f,v")))
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_VX && TARGET_HARD_FLOAT
- && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)"
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
- cl<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1,0
- wcl<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2"
+ cl<gf><xde>br\t%0,%h2,%1,0
+ wcl<gf><xde>b\t%v0,%v1,0,%h2"
[(set_attr "op_type" "RRF,VRR")
(set_attr "type" "ftoi")])
@@ -5305,16 +5307,15 @@
; df -> signed di, vxe2: sf -> signed si
; cgdbr, cfebr, wcgdb, wcfeb
-(define_insn "*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13"
- [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v")
- (fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v")))
- (unspec:VX_CONV_INT [(match_operand:VX_CONV_INT 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
+(define_insn "*fix_trunc<mode><toint>2_bfp_z13"
+ [(set (match_operand:<TOINT> 0 "register_operand" "=d,v")
+ (fix:<TOINT> (match_operand:VX_CONV_BFP 1 "register_operand" "f,v")))
+ (unspec:<TOINT> [(match_operand:<TOINT> 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_VX && TARGET_HARD_FLOAT
- && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)"
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
- c<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1
- wc<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2"
+ c<gf><xde>br\t%0,%h2,%1
+ wc<gf><xde>b\t%v0,%v1,0,%h2"
[(set_attr "op_type" "RRE,VRR")
(set_attr "type" "ftoi")])
@@ -5420,14 +5421,13 @@
; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
;
-(define_insn "*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13"
- [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v")
- (unsigned_float:VX_CONV_BFP (match_operand:VX_CONV_INT 1 "register_operand" "d,v")))]
- "TARGET_VX && TARGET_HARD_FLOAT
- && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)"
+(define_insn "*floatuns<toint><mode>2_z13"
+ [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v")
+ (unsigned_float:VX_CONV_BFP (match_operand:<TOINT> 1 "register_operand" "d,v")))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
- c<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>br\t%0,0,%1,0
- wc<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>b\t%v0,%v1,0,0"
+ c<xde>l<gf>br\t%0,0,%1,0
+ wc<xde>l<gf>b\t%v0,%v1,0,0"
[(set_attr "op_type" "RRE,VRR")
(set_attr "type" "itofdf")])
@@ -7568,7 +7568,7 @@
; div(df|sf)3 instruction pattern(s).
;
-; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
+; dxbr, ddbr, debr, ddb, deb, ddtr, dxtr
(define_insn "div<mode>3<tf_fpr>"
[(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
(div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
@@ -86,7 +86,6 @@
; 32 bit int<->fp vector conversion instructions are available since VXE2 (z15).
(define_mode_iterator VX_VEC_CONV_BFP [V2DF (V4SF "TARGET_VXE2")])
-(define_mode_iterator VX_VEC_CONV_INT [V2DI (V4SI "TARGET_VXE2")])
; Empty string for all but TImode. This is used to hide the TImode
; expander name in case it is defined already. See addti3 for an
@@ -2508,12 +2507,11 @@
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: according to current rounding mode
; vcdgb, vcefb
-(define_insn "float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2"
- [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v")
- (float:VX_VEC_CONV_BFP (match_operand:VX_VEC_CONV_INT 1 "register_operand" "v")))]
- "TARGET_VX
- && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)"
- "vc<VX_VEC_CONV_BFP:xde><VX_VEC_CONV_INT:bhfgq>b\t%v0,%v1,0,0"
+(define_insn "float<tointvec><mode>2"
+ [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v")
+ (float:VX_VEC_CONV_BFP (match_operand:<TOINTVEC> 1 "register_operand" "v")))]
+ "TARGET_VX"
+ "vc<xde><bhfgq>b\t%v0,%v1,0,0"
[(set_attr "op_type" "VRR")])
; There is no instruction for loading a signed integer into an extended BFP
@@ -2539,12 +2537,11 @@
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: according to current rounding mode
; vcdlgb, vcelfb
-(define_insn "floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2"
- [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v")
- (unsigned_float:VX_VEC_CONV_BFP (match_operand:VX_VEC_CONV_INT 1 "register_operand" "v")))]
- "TARGET_VX
- && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)"
- "vc<VX_VEC_CONV_BFP:xde>l<VX_VEC_CONV_INT:bhfgq>b\t%v0,%v1,0,0"
+(define_insn "floatuns<tointvec><mode>2"
+ [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v")
+ (unsigned_float:VX_VEC_CONV_BFP (match_operand:<TOINTVEC> 1 "register_operand" "v")))]
+ "TARGET_VX"
+ "vc<xde>l<bhfgq>b\t%v0,%v1,0,0"
[(set_attr "op_type" "VRR")])
; There is no instruction for loading an unsigned integer into an extended BFP
@@ -2570,12 +2567,11 @@
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: rounding mode 5 (round towards 0 C11 6.3.1.4)
; vcgdb, vcfeb
-(define_insn "fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2"
- [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "=v")
- (fix:VX_VEC_CONV_INT (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))]
- "TARGET_VX
- && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)"
- "vc<VX_VEC_CONV_INT:bhfgq><VX_VEC_CONV_BFP:xde>b\t%v0,%v1,0,5"
+(define_insn "fix_trunc<mode><tointvec>2"
+ [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v")
+ (fix:<TOINTVEC> (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))]
+ "TARGET_VX"
+ "vc<bhfgq><xde>b\t%v0,%v1,0,5"
[(set_attr "op_type" "VRR")])
; There is no instruction for rounding an extended BFP operand in a VR into
@@ -2604,12 +2600,11 @@
; op2: inexact exception not suppressed (IEEE 754 2008)
; op3: rounding mode 5 (round towards 0 C11 6.3.1.4)
; vclgdb, vclfeb
-(define_insn "fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2"
- [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "=v")
- (unsigned_fix:VX_VEC_CONV_INT (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))]
- "TARGET_VX
- && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)"
- "vcl<VX_VEC_CONV_INT:bhfgq><VX_VEC_CONV_BFP:xde>b\t%v0,%v1,0,5"
+(define_insn "fixuns_trunc<VX_VEC_CONV_BFP:mode><tointvec>2"
+ [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v")
+ (unsigned_fix:<TOINTVEC> (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))]
+ "TARGET_VX"
+ "vcl<bhfgq><xde>b\t%v0,%v1,0,5"
[(set_attr "op_type" "VRR")])
; There is no instruction for rounding an extended BFP operand in a VR into