diff mbox series

minimal support for xtheadv

Message ID 20231108131237.3672914-1-chenyixuan@iscas.ac.cn
State Unresolved
Headers
Series minimal support for xtheadv |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

陈逸轩 Nov. 8, 2023, 1:12 p.m. UTC 
  From: XYenChi <oriachiuan@gmail.com>

This patch is for support xtheadv.

gcc/ChangeLog:

2023-11-08  Chen Yixuan  <chenyixuan@iscas.an.cn>

        * common/config/riscv/riscv-common.cc: Add xthead minimal support.

gcc/config/ChangeLog:

2023-11-08  Chen Yixuan  <chenyixuan@iscas.an.cn>

        * riscv/riscv.opt: Add xthead minimal support.
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv.opt              | 2 ++
 2 files changed, 4 insertions(+)

Comments

Christoph Müllner Nov. 9, 2023, 8:05 a.m. UTC | #1 
On Thu, Nov 9, 2023 at 8:39 AM Kito Cheng <kito.cheng@gmail.com> wrote:
>
> Hi Yi Xuan:
>
> This patch is trivial, and generally LGTM, but I would require putting
> the spec into https://github.com/riscv-non-isa/riscv-toolchain-conventions
> before merging this, also don't forget include "RISC-V:" in the title,
> it would be easier to track during the RISC-V GCC sync meeting :)
>
> And I am a little bit confused by the author's info? is it from you or
> "XYenChi <oriachiuan@gmail.com>"? or oriachiuan@gmail.com is also your
> mail address?
>
> cc Christoph since I believe you may know more about that process.
> cc JoJo since you are T-head folk :P

Hi Yi Xuan and Kito,

I was not aware that CAS is working on getting T-Head's Vector
extension supported.
My biggest concern with this patch is that "XTheadV" does not have a
specification.

T-Head and VRULL are currently working on support patches for T-Head's
Vector extension
implementation. We've named the extension XTheadVector.
Supporting XTheadVector means to address a range of issues (e.g.
defining a formal ISA
vendor extension specification, extension discovery, addressing
implementation details,
differences among available cores, intrinsics, ...).
We've already made good progress on that and expect to publish first
results soon.

BR
Christoph

>
>
> On Wed, Nov 8, 2023 at 9:13 PM <chenyixuan@iscas.ac.cn> wrote:
> >
> > From: XYenChi <oriachiuan@gmail.com>
> >
> > This patch is for support xtheadv.
> >
> > gcc/ChangeLog:
> >
> > 2023-11-08  Chen Yixuan  <chenyixuan@iscas.an.cn>
> >
> >         * common/config/riscv/riscv-common.cc: Add xthead minimal support.
> >
> > gcc/config/ChangeLog:
> >
> > 2023-11-08  Chen Yixuan  <chenyixuan@iscas.an.cn>
> >
> >         * riscv/riscv.opt: Add xthead minimal support.
> > ---
> >  gcc/common/config/riscv/riscv-common.cc | 2 ++
> >  gcc/config/riscv/riscv.opt              | 2 ++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> > index 526dbb7603b..d5ea0ee9b70 100644
> > --- a/gcc/common/config/riscv/riscv-common.cc
> > +++ b/gcc/common/config/riscv/riscv-common.cc
> > @@ -325,6 +325,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
> >    {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
> >    {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
> >    {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
> > +  {"xtheadv",    ISA_SPEC_CLASS_NONE, 0, 7},
> >
> >    {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
> >
> > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
> >    {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
> >    {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
> >    {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
> > +  {"xtheadv",       &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV},
> >
> >    {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
> >
> > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> > index 70d78151cee..2bbdf680fa2 100644
> > --- a/gcc/config/riscv/riscv.opt
> > +++ b/gcc/config/riscv/riscv.opt
> > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
> >
> >  Mask(XTHEADSYNC)    Var(riscv_xthead_subext)
> >
> > +Mask(XTHEADV)       Var(riscv_xthead_subext)
> > +
> >  TargetVariable
> >  int riscv_xventana_subext
> >
> > --
> > 2.42.0
> >
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..d5ea0ee9b70 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -325,6 +325,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadv",    ISA_SPEC_CLASS_NONE, 0, 7},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1680,6 +1681,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadv",       &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV},
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..2bbdf680fa2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -438,6 +438,8 @@  Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)    Var(riscv_xthead_subext)
 
+Mask(XTHEADV)       Var(riscv_xthead_subext)
+
 TargetVariable
 int riscv_xventana_subext