Message ID | 20231107080436.16747-1-krzysztof.kozlowski@linaro.org |
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State | New |
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([178.197.218.126]) by smtp.gmail.com with ESMTPSA id x16-20020aa7d6d0000000b00532eba07773sm5049106edr.25.2023.11.07.00.04.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 00:04:38 -0800 (PST) From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH] dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries Date: Tue, 7 Nov 2023 09:04:36 +0100 Message-Id: <20231107080436.16747-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 07 Nov 2023 00:04:48 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781891637881048785 X-GMAIL-MSGID: 1781891637881048785 |
Series |
dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries
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Commit Message
Krzysztof Kozlowski
Nov. 7, 2023, 8:04 a.m. UTC
Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by
dtbs_check:
qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:2: 'llcc2_base' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Recent LLCC patches were not tested on QDU1000 thus the LLCC is there
broken. This patch at least tries to bring some sense according to
DTSI, but I have no clue what is here correct: driver, DTS or bindings.
---
Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 11/7/2023 1:34 PM, Krzysztof Kozlowski wrote: > Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by > dtbs_check: > > qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:2: 'llcc2_base' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Recent LLCC patches were not tested on QDU1000 thus the LLCC is there > broken. This patch at least tries to bring some sense according to > DTSI, but I have no clue what is here correct: driver, DTS or bindings. > --- > Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > index 580f9a97ddf7..d610b0be262c 100644 > --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > @@ -64,6 +64,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,qdu1000-llcc > - qcom,sc7180-llcc > - qcom,sm6350-llcc Thanks, again. Acked-by: Mukesh Ojha <quic_mojha@quicinc.com> -Mukesh > then: > @@ -101,7 +102,6 @@ allOf: > compatible: > contains: > enum: > - - qcom,qdu1000-llcc > - qcom,sc8180x-llcc > - qcom,sc8280xp-llcc > then:
On Tue, Nov 07, 2023 at 02:25:25PM +0530, Mukesh Ojha wrote: > > > On 11/7/2023 1:34 PM, Krzysztof Kozlowski wrote: > > Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by > > dtbs_check: > > > > qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:2: 'llcc2_base' was expected > > > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > > --- > > > > Recent LLCC patches were not tested on QDU1000 thus the LLCC is there > > broken. This patch at least tries to bring some sense according to > > DTSI, but I have no clue what is here correct: driver, DTS or bindings. > > --- > > Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > > index 580f9a97ddf7..d610b0be262c 100644 > > --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > > +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml > > @@ -64,6 +64,7 @@ allOf: > > compatible: > > contains: > > enum: > > + - qcom,qdu1000-llcc > > - qcom,sc7180-llcc > > - qcom,sm6350-llcc > > Thanks, again. > > Acked-by: Mukesh Ojha <quic_mojha@quicinc.com> I'm assuming given your employer, this ack means that there is no llcc2_base on the qdu1000. Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On 11/8/2023 5:56 PM, Conor Dooley wrote: > On Tue, Nov 07, 2023 at 02:25:25PM +0530, Mukesh Ojha wrote: >> >> >> On 11/7/2023 1:34 PM, Krzysztof Kozlowski wrote: >>> Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by >>> dtbs_check: >>> >>> qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:2: 'llcc2_base' was expected >>> >>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> >>> --- >>> >>> Recent LLCC patches were not tested on QDU1000 thus the LLCC is there >>> broken. This patch at least tries to bring some sense according to >>> DTSI, but I have no clue what is here correct: driver, DTS or bindings. >>> --- >>> Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml >>> index 580f9a97ddf7..d610b0be262c 100644 >>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml >>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml >>> @@ -64,6 +64,7 @@ allOf: >>> compatible: >>> contains: >>> enum: >>> + - qcom,qdu1000-llcc >>> - qcom,sc7180-llcc >>> - qcom,sm6350-llcc >> >> Thanks, again. >> >> Acked-by: Mukesh Ojha <quic_mojha@quicinc.com> > > I'm assuming given your employer, this ack means that there is no > llcc2_base on the qdu1000. Yes, not even have llcc1 , just llcc0. -Mukesh > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor.
On Tue, 07 Nov 2023 09:04:36 +0100, Krzysztof Kozlowski wrote: > Qualcomm QDU1000 DTSI comes with one LLCC0 base address as pointed by > dtbs_check: > > qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:2: 'llcc2_base' was expected > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Recent LLCC patches were not tested on QDU1000 thus the LLCC is there > broken. This patch at least tries to bring some sense according to > DTSI, but I have no clue what is here correct: driver, DTS or bindings. > --- > Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 580f9a97ddf7..d610b0be262c 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -64,6 +64,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sm6350-llcc then: @@ -101,7 +102,6 @@ allOf: compatible: contains: enum: - - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: