Message ID | 20231102193722.3042245-4-ben.wolsieffer@hefring.com |
---|---|
State | New |
Headers |
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Thu, 02 Nov 2023 12:38:01 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id a10-20020a0ce90a000000b0065b260eafd9sm30654qvo.87.2023.11.02.12.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 12:38:00 -0700 (PDT) From: Ben Wolsieffer <ben.wolsieffer@hefring.com> To: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue <alexandre.torgue@foss.st.com>, Alain Volmat <alain.volmat@foss.st.com>, Erwan Leray <erwan.leray@foss.st.com>, Fabrice Gasnier <fabrice.gasnier@foss.st.com>, Ben Wolsieffer <ben.wolsieffer@hefring.com> Subject: [PATCH v2 3/5] dt-bindings: spi: add stm32f7-spi compatible Date: Thu, 2 Nov 2023 15:37:20 -0400 Message-ID: <20231102193722.3042245-4-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> References: <20231102193722.3042245-1-ben.wolsieffer@hefring.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); 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Series | Add STM32F7 SPI support | |
Commit Message
Ben Wolsieffer
Nov. 2, 2023, 7:37 p.m. UTC
The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the
only significant differences being support for a wider range of word
sizes and the addition of 32-bit transmit and receive FIFOs.
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
---
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 1 +
1 file changed, 1 insertion(+)
Comments
On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote: > The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the > only significant differences being support for a wider range of word > sizes and the addition of 32-bit transmit and receive FIFOs. A wider range of supported word sizes and some additional buffers, implies that the F4 could be used as a fallback compatible. Does the register map change incompatibly in the process of widening the FIFOs or something like that? Cheers, Conor. > > Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> > --- > Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml > index ae0f082bd377..5754d603f34f 100644 > --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml > +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml > @@ -23,6 +23,7 @@ properties: > compatible: > enum: > - st,stm32f4-spi > + - st,stm32f7-spi > - st,stm32h7-spi > > reg: > -- > 2.42.0 >
Hi Conor, On Fri, Nov 03, 2023 at 12:50:53PM +0000, Conor Dooley wrote: > On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote: > A wider range of supported word sizes and some additional buffers, > implies that the F4 could be used as a fallback compatible. Does the > register map change incompatibly in the process of widening the FIFOs or > something like that? Yes, the F4 has a single bit to select 8 or 16 bit word size, while the F7 uses four bits to select an arbitrary word size from 4 to 16 bits. This series supports the packing mode, to allow sending two <=8 bit words with a single write to the FIFO, but even if we didn't want to support this feature, the F7 would require setting the FRXTH bit (not present in the F4) when using <=8 bit word sizes. > > Cheers, > Conor.
On Fri, Nov 03, 2023 at 09:29:12AM -0400, Ben Wolsieffer wrote: > Hi Conor, > > On Fri, Nov 03, 2023 at 12:50:53PM +0000, Conor Dooley wrote: > > On Thu, Nov 02, 2023 at 03:37:20PM -0400, Ben Wolsieffer wrote: > > A wider range of supported word sizes and some additional buffers, > > implies that the F4 could be used as a fallback compatible. Does the > > register map change incompatibly in the process of widening the FIFOs or > > something like that? > > Yes, the F4 has a single bit to select 8 or 16 bit word size, while the > F7 uses four bits to select an arbitrary word size from 4 to 16 bits. > This series supports the packing mode, to allow sending two <=8 bit > words with a single write to the FIFO, but even if we didn't want to > support this feature, the F7 would require setting the FRXTH bit (not > present in the F4) when using <=8 bit word sizes. Oke. Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index ae0f082bd377..5754d603f34f 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - st,stm32f4-spi + - st,stm32f7-spi - st,stm32h7-spi reg: