Message ID | 20231031120307.1600689-3-quic_mdalam@quicinc.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b90f:0:b0:403:3b70:6f57 with SMTP id t15csp184352vqg; Tue, 31 Oct 2023 05:04:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEqV8+b0NobO7Fei91TdIn25BK0Emh8d1yT7B90XNjjOlFCHY8WWvF3p6eZocrGDJDXieqW X-Received: by 2002:a17:903:22c3:b0:1cc:478c:2f32 with SMTP id y3-20020a17090322c300b001cc478c2f32mr5025197plg.0.1698753890638; Tue, 31 Oct 2023 05:04:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698753890; cv=none; d=google.com; s=arc-20160816; b=OKypOEaqRtQlqhKLQbPYNdCja+oZ0pPpLsLqOKyDZeoiJZ+rJ7RVFmS1t7hzNmnrLu exB4XB9HvmlWes/XqCy8rPZrH5el1KeUbU+CBjx9RcOpUdW0jAe71l9h/yv87jC/uRFN xCDMN6IyTnYsPDTUD5dH0R9dPlmXDgmP4Y8WleVejwX/2WcoL0Aosk8fImLdPLqkL4md ha/Uh/vyLJ+zPi5sVXHXa5X3Zdy1ggqoRmv70MJd5U4Z8H6sJCvNQx+vGYfaUN60E7a0 t1BhQY25aKWNWePpNI4qYicgZBxiaLbjRsHz6zNyUNlrvKdsSsmU+Innux1qk3DM1+j2 YcBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Rz7FoOgVVF6qLGQwCv68miCnmwfmImZT149I8dxHdBY=; fh=gv5Z3UYh4OJrEQHzuaRSDOa6LHGr3r586M32+msCC1g=; b=krGALJaO1HkvqXU1zrf7/J10R8sWtAE5AqmSQmhwXLxX+Oro+0bawOPX565MXIxmQ6 t55gUhyofItUxMzIoCrCjGs0TXnpY8LLNnf6bg7/dK8u0QJpIlO1EGrwooWK+VRZ2bYp 0JMSEPmX+67ZRyJadJ9dypRzrUnp+cJT9jzfUUu367DEPGehPztfZvW+p7r93qj1C8MQ xdWUqjTEwdAo9chl0UgGLdD2zcYH5n8aFEceZmwvBYForA+9+Z01TnQ3Q4T9yD4FTnuX oRpS1qw/lPi5SGUF8OLoCs0irXS7ivPJspr5UxzA7O2vPrm884JDmzuhLJZ/1mdeeX6X m8FQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=J7EKT5Z0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id s7-20020a170903320700b001b84335fb90si904751plh.286.2023.10.31.05.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 05:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=J7EKT5Z0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 6606880C9A60; Tue, 31 Oct 2023 05:04:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344160AbjJaMEO (ORCPT <rfc822;chrisjones.unixmen@gmail.com> + 33 others); Tue, 31 Oct 2023 08:04:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344195AbjJaMEB (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 31 Oct 2023 08:04:01 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E51645587; Tue, 31 Oct 2023 05:03:59 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39VAAtxE025495; Tue, 31 Oct 2023 12:03:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=Rz7FoOgVVF6qLGQwCv68miCnmwfmImZT149I8dxHdBY=; b=J7EKT5Z0XD9PilD5oWKjprMK7zeVntNbEdBQlUIHV6X79pDSCJDQ4N+y85F60BjmWmek 1rSH4sOndSZnzYjjBnv1Vs3/7STBzneI4fwG41wAc5+4jx6r5W0b25kg0+7/ECcQeiBW uXiHsOrgtVVoUi2+3ThM5XZEbCSbfXVJ5+tBoant8taEYKuYM7y8hX/i28uoHNURS35S BgF+ZkjYHOIRU268SSXTYYhfTBjs9h+5GK8eYjUW9MIWWQuJPiQ4Lz1r5cXSFAZ4s0I5 jiP4K8eL6ytmnVAnYB3elMX8rbn3KKfo+cf/8yX2t+jCDy01KIYjrvyhTAgDUQpOL6l4 4Q== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u2fuvjc1q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Oct 2023 12:03:14 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39VC3B9Q005273; Tue, 31 Oct 2023 12:03:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3u0uckvvp9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Oct 2023 12:03:11 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39VC3BKb005266; Tue, 31 Oct 2023 12:03:11 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 39VC3BGf005265 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Oct 2023 12:03:11 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 5382A414B1; Tue, 31 Oct 2023 17:33:10 +0530 (+0530) From: Md Sadre Alam <quic_mdalam@quicinc.com> To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, quic_srichara@quicinc.com, qpic_varada@quicinc.com Cc: quic_mdalam@quicinc.com Subject: [RFC PATCH 2/5] arm64: dts: qcom: ipq9574: Add ecc engine support Date: Tue, 31 Oct 2023 17:33:04 +0530 Message-Id: <20231031120307.1600689-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231031120307.1600689-1-quic_mdalam@quicinc.com> References: <20231031120307.1600689-1-quic_mdalam@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9sWzIsBXCgwtCbL1n4tm2kR0MpwZAYIK X-Proofpoint-GUID: 9sWzIsBXCgwtCbL1n4tm2kR0MpwZAYIK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-31_01,2023-10-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 phishscore=0 mlxlogscore=684 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310094 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 31 Oct 2023 05:04:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781272559306631787 X-GMAIL-MSGID: 1781272559306631787 |
Series |
Add QPIC SPI NAND driver support
|
|
Commit Message
Md Sadre Alam
Oct. 31, 2023, 12:03 p.m. UTC
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
Comments
On 31.10.2023 13:03, Md Sadre Alam wrote: > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > --- Hello, you're missing: - dt-bindings (make dtbs_check is unhappy) - a commit message - Co-developed-by for Sricharan status should read "okay" instead, but in this case it's unnecessary as you're defining the node and lack of the status property also means that device is enabled however this ECC engine seems to be a part of the NAND controller, so it's unlikely that the DT maintainers will agree for it to have a separate node Konrad > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 5f83ee42a719..b44acb1fac74 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -336,6 +336,11 @@ sdhc_1: mmc@7804000 { > status = "disabled"; > }; > > + bch: qpic_ecc { > + compatible = "qcom,ipq9574-ecc"; > + status = "ok"; > + } > + > blsp_dma: dma-controller@7884000 { > compatible = "qcom,bam-v1.7.0"; > reg = <0x07884000 0x2b000>;
On 31/10/2023 13:03, Md Sadre Alam wrote: > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > --- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 5f83ee42a719..b44acb1fac74 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -336,6 +336,11 @@ sdhc_1: mmc@7804000 { > status = "disabled"; > }; > > + bch: qpic_ecc { > + compatible = "qcom,ipq9574-ecc"; NAK. There are so many wrong things with it... Let's start with missing checkpatch. Then with unndeeded label. Then with not allowed underscores in node names. Finally: > + status = "ok"; Drop. Best regards, Krzysztof
On 10/31/2023 8:53 PM, Konrad Dybcio wrote: > On 31.10.2023 13:03, Md Sadre Alam wrote: >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> >> --- > Hello, > > you're missing: > > - dt-bindings (make dtbs_check is unhappy) > - a commit message > - Co-developed-by for Sricharan > > status should read "okay" instead, but in this case it's unnecessary > as you're defining the node and lack of the status property also means > that device is enabled > > however > > this ECC engine seems to be a part of the NAND controller, so it's > unlikely that the DT maintainers will agree for it to have a separate > node > Will drop this patch as this was NAK-ed QPIC controller has the ecc pipelined so will keep the ecc support inlined in both raw nand and serial nand driver. Regards Alam.
On 10/31/2023 10:42 PM, Krzysztof Kozlowski wrote: > On 31/10/2023 13:03, Md Sadre Alam wrote: >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> >> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 5f83ee42a719..b44acb1fac74 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -336,6 +336,11 @@ sdhc_1: mmc@7804000 { >> status = "disabled"; >> }; >> >> + bch: qpic_ecc { >> + compatible = "qcom,ipq9574-ecc"; > > NAK. There are so many wrong things with it... Let's start with missing > checkpatch. Then with unndeeded label. Then with not allowed underscores > in node names. > Finally: >> + status = "ok"; > > Drop. > Ok > > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5f83ee42a719..b44acb1fac74 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -336,6 +336,11 @@ sdhc_1: mmc@7804000 { status = "disabled"; }; + bch: qpic_ecc { + compatible = "qcom,ipq9574-ecc"; + status = "ok"; + } + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x2b000>;