@@ -107,6 +107,9 @@ (define_constraint "wB"
(match_test "TARGET_P8_VECTOR")
(match_operand 0 "s5bit_cint_operand")))
+(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]"
+ "Accumulator register.")
+
(define_constraint "wE"
"@internal Vector constant that can be loaded with the XXSPLTIB instruction."
(match_test "xxspltib_constant_nosplit (op, mode)"))
@@ -92,6 +92,7 @@ (define_c_enum "unspec"
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_VECTOR_PAIR_MEMORY
+ UNSPEC_DM_ASSEMBLE_ACC
])
(define_c_enum "unspecv"
@@ -358,7 +359,9 @@ (define_insn_and_split "*vector_pair_memory_builtin"
(set_attr "length" "*,*,8")])
-;; Vector quad support. XOmode can only live in FPRs.
+;; Vector quad support. Under the original MMA, XOmode can only live in VSX
+;; vector registers 0..31. With dense math, XOmode can live in either VSX
+;; registers (0..63) or DMR registers.
(define_expand "movxo"
[(set (match_operand:XO 0 "nonimmediate_operand")
(match_operand:XO 1 "input_operand"))]
@@ -383,10 +386,10 @@ (define_expand "movxo"
gcc_assert (false);
})
-(define_insn_and_split "*movxo"
+(define_insn_and_split "*movxo_nodm"
[(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
(match_operand:XO 1 "input_operand" "ZwO,d,d"))]
- "TARGET_MMA
+ "TARGET_MMA && !TARGET_DENSE_MATH
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
"@
@@ -403,6 +406,31 @@ (define_insn_and_split "*movxo"
(set_attr "length" "*,*,16")
(set_attr "max_prefixed_insns" "2,2,*")])
+(define_insn_and_split "*movxo_dm"
+ [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,QwO,wa,wD,wD,wa")
+ (match_operand:XO 1 "input_operand" "QwO,wa, wa,wa,wD,wD"))]
+ "TARGET_DENSE_MATH
+ && (gpc_reg_operand (operands[0], XOmode)
+ || gpc_reg_operand (operands[1], XOmode))"
+ "@
+ #
+ #
+ #
+ dmxxinstdmr512 %0,%1,%Y1,0
+ dmmr %0,%1
+ dmxxextfdmr512 %0,%Y0,%1,0"
+ "&& reload_completed
+ && !dmr_operand (operands[0], XOmode)
+ && !dmr_operand (operands[1], XOmode)"
+ [(const_int 0)]
+{
+ rs6000_split_multireg_move (operands[0], operands[1]);
+ DONE;
+}
+ [(set_attr "type" "vecload,vecstore,veclogical,mma,mma,mma")
+ (set_attr "length" "*,*,16,*,*,*")
+ (set_attr "max_prefixed_insns" "2,2,*,*,*,*")])
+
(define_expand "vsx_assemble_pair"
[(match_operand:OO 0 "vsx_register_operand")
(match_operand:V16QI 1 "mma_assemble_input_operand")
@@ -470,25 +498,38 @@ (define_insn_and_split "*vsx_disassemble_pair"
})
(define_expand "mma_assemble_acc"
- [(match_operand:XO 0 "fpr_reg_operand")
+ [(match_operand:XO 0 "register_operand")
(match_operand:V16QI 1 "mma_assemble_input_operand")
(match_operand:V16QI 2 "mma_assemble_input_operand")
(match_operand:V16QI 3 "mma_assemble_input_operand")
(match_operand:V16QI 4 "mma_assemble_input_operand")]
"TARGET_MMA"
{
- rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode,
- gen_rtvec (4, operands[1], operands[2],
- operands[3], operands[4]),
- UNSPECV_MMA_ASSEMBLE);
- emit_move_insn (operands[0], src);
+ rtx op0 = operands[0];
+ rtx op1 = operands[1];
+ rtx op2 = operands[2];
+ rtx op3 = operands[3];
+ rtx op4 = operands[4];
+
+ if (TARGET_DENSE_MATH)
+ {
+ rtx vpair1 = gen_reg_rtx (OOmode);
+ rtx vpair2 = gen_reg_rtx (OOmode);
+ emit_insn (gen_vsx_assemble_pair (vpair1, op1, op2));
+ emit_insn (gen_vsx_assemble_pair (vpair2, op3, op4));
+ emit_insn (gen_mma_assemble_acc_dm (op0, vpair1, vpair2));
+ }
+
+ else
+ emit_insn (gen_mma_assemble_acc_vsx (op0, op1, op2, op3, op4));
+
DONE;
})
;; We cannot update the four output registers atomically, so mark the output
-;; as an early clobber so we don't accidentally clobber the input operands. */
+;; as an early clobber so we don't accidentally clobber the input operands.
-(define_insn_and_split "*mma_assemble_acc"
+(define_insn_and_split "mma_assemble_acc_vsx"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
(unspec_volatile:XO
[(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa")
@@ -496,7 +537,7 @@ (define_insn_and_split "*mma_assemble_acc"
(match_operand:V16QI 3 "mma_assemble_input_operand" "mwa")
(match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")]
UNSPECV_MMA_ASSEMBLE))]
- "TARGET_MMA
+ "TARGET_MMA && !TARGET_DENSE_MATH
&& fpr_reg_operand (operands[0], XOmode)"
"#"
"&& reload_completed"
@@ -510,28 +551,31 @@ (define_insn_and_split "*mma_assemble_acc"
DONE;
})
+;; On a system with dense math, we build the accumulators from two vector
+;; pairs.
+
+(define_insn "mma_assemble_acc_dm"
+ [(set (match_operand:XO 0 "dmr_operand" "=wD")
+ (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa")
+ (match_operand:OO 2 "vsx_register_operand" "wa")]
+ UNSPEC_DM_ASSEMBLE_ACC))]
+ "TARGET_MMA && TARGET_DENSE_MATH"
+ "dmxxinstdmr512 %0,%1,%2,0"
+ [(set_attr "type" "mma")])
+
(define_expand "mma_disassemble_acc"
- [(match_operand:V16QI 0 "mma_disassemble_output_operand")
- (match_operand:XO 1 "fpr_reg_operand")
- (match_operand 2 "const_0_to_3_operand")]
- "TARGET_MMA"
-{
- rtx src;
- int regoff = INTVAL (operands[2]);
- src = gen_rtx_UNSPEC (V16QImode,
- gen_rtvec (2, operands[1], GEN_INT (regoff)),
- UNSPEC_MMA_EXTRACT);
- emit_move_insn (operands[0], src);
- DONE;
-})
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand:XO 1 "register_operand")
+ (match_operand 2 "const_0_to_3_operand")]
+ UNSPEC_MMA_EXTRACT))]
+ "TARGET_MMA")
-(define_insn_and_split "*mma_disassemble_acc"
+(define_insn_and_split "*mma_disassemble_acc_vsx"
[(set (match_operand:V16QI 0 "mma_disassemble_output_operand" "=mwa")
- (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
- (match_operand 2 "const_0_to_3_operand")]
+ (unspec:V16QI [(match_operand:XO 1 "fpr_reg_operand" "d")
+ (match_operand 2 "const_0_to_3_operand")]
UNSPEC_MMA_EXTRACT))]
- "TARGET_MMA
- && fpr_reg_operand (operands[1], XOmode)"
+ "TARGET_MMA"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -543,9 +587,14 @@ (define_insn_and_split "*mma_disassemble_acc"
DONE;
})
-;; MMA instructions that do not use their accumulators as an input, still
-;; must not allow their vector operands to overlap the registers used by
-;; the accumulator. We enforce this by marking the output as early clobber.
+(define_insn "*mma_disassemble_acc_dm"
+ [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+ (unspec:V16QI [(match_operand:XO 1 "dmr_operand" "wD")
+ (match_operand 2 "const_0_to_3_operand")]
+ UNSPEC_MMA_EXTRACT))]
+ "TARGET_DENSE_MATH"
+ "dmxxextfdmr256 %0,%1,2"
+ [(set_attr "type" "mma")])
(define_insn "mma_<acc>"
[(set (match_operand:XO 0 "fpr_reg_operand" "=&d")
@@ -186,6 +186,38 @@ (define_predicate "vlogical_operand"
return VLOGICAL_REGNO_P (REGNO (op));
})
+;; Return 1 if op is a DMR register
+(define_predicate "dmr_operand"
+ (match_operand 0 "register_operand")
+{
+ if (!REG_P (op))
+ return 0;
+
+ if (!HARD_REGISTER_P (op))
+ return 1;
+
+ return DMR_REGNO_P (REGNO (op));
+})
+
+;; Return 1 if op is an accumulator. On power10 systems, the accumulators
+;; overlap with the FPRs, while on systems with dense math, the accumulators
+;; are separate dense math registers and do not overlap with the FPR
+;; registers..
+(define_predicate "accumulator_operand"
+ (match_operand 0 "register_operand")
+{
+ if (!REG_P (op))
+ return 0;
+
+ if (!HARD_REGISTER_P (op))
+ return 1;
+
+ int r = REGNO (op);
+ return (TARGET_DENSE_MATH
+ ? DMR_REGNO_P (r)
+ : FP_REGNO_P (r) && (r & 3) == 0);
+})
+
;; Return 1 if op is the carry register.
(define_predicate "ca_operand"
(match_operand 0 "register_operand")
@@ -91,6 +91,7 @@
/* Flags for a potential future processor that may or may not be delivered. */
#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \
| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
+ | OPTION_MASK_DENSE_MATH \
| OPTION_MASK_FUTURE)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -134,6 +135,7 @@
| OPTION_MASK_DFP \
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_DLMZB \
+ | OPTION_MASK_DENSE_MATH \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
@@ -290,7 +290,8 @@ enum rs6000_reg_type {
ALTIVEC_REG_TYPE,
FPR_REG_TYPE,
SPR_REG_TYPE,
- CR_REG_TYPE
+ CR_REG_TYPE,
+ DMR_REG_TYPE
};
/* Map register class to register type. */
@@ -304,22 +305,23 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
/* Register classes we care about in secondary reload or go if legitimate
- address. We only need to worry about GPR, FPR, and Altivec registers here,
- along an ANY field that is the OR of the 3 register classes. */
+ address. We only need to worry about GPR, FPR, Altivec, and DMR registers
+ here, along an ANY field that is the OR of the 4 register classes. */
enum rs6000_reload_reg_type {
RELOAD_REG_GPR, /* General purpose registers. */
RELOAD_REG_FPR, /* Traditional floating point regs. */
RELOAD_REG_VMX, /* Altivec (VMX) registers. */
- RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
+ RELOAD_REG_DMR, /* DMR registers. */
+ RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMR masks. */
N_RELOAD_REG
};
-/* For setting up register classes, loop through the 3 register classes mapping
+/* For setting up register classes, loop through the 4 register classes mapping
into real registers, and skip the ANY class, which is just an OR of the
bits. */
#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
-#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
+#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMR
/* Map reload register type to a register in the register class. */
struct reload_reg_map_type {
@@ -331,6 +333,7 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
{ "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
{ "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
{ "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
+ { "DMR", FIRST_DMR_REGNO }, /* RELOAD_REG_DMR. */
{ "Any", -1 }, /* RELOAD_REG_ANY. */
};
@@ -1224,6 +1227,8 @@ char rs6000_reg_names[][8] =
"0", "1", "2", "3", "4", "5", "6", "7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
+ /* DMRs */
+ "0", "1", "2", "3", "4", "5", "6", "7",
};
#ifdef TARGET_REGNAMES
@@ -1250,6 +1255,8 @@ static const char alt_reg_names[][8] =
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
/* vrsave vscr sfp */
"vrsave", "vscr", "sfp",
+ /* DMRs */
+ "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7",
};
#endif
@@ -1837,6 +1844,9 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
else if (ALTIVEC_REGNO_P (regno))
reg_size = UNITS_PER_ALTIVEC_WORD;
+ else if (DMR_REGNO_P (regno))
+ reg_size = UNITS_PER_DMR_WORD;
+
else
reg_size = UNITS_PER_WORD;
@@ -1858,9 +1868,36 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
if (mode == OOmode)
return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0);
- /* MMA accumulator modes need FPR registers divisible by 4. */
+ /* On ISA 3.1 (power10), MMA accumulator modes need FPR registers divisible
+ by 4.
+
+ If dense math is enabled, allow all VSX registers plus the DMR registers.
+ We need to make sure we don't cross between the boundary of FPRs and
+ traditional Altiviec registers. */
if (mode == XOmode)
- return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);
+ {
+ if (TARGET_MMA && !TARGET_DENSE_MATH)
+ return (FP_REGNO_P (regno) && (regno & 3) == 0);
+
+ else if (TARGET_DENSE_MATH)
+ {
+ if (DMR_REGNO_P (regno))
+ return 1;
+
+ if (FP_REGNO_P (regno))
+ return ((regno & 1) == 0 && regno <= LAST_FPR_REGNO - 3);
+
+ if (ALTIVEC_REGNO_P (regno))
+ return ((regno & 1) == 0 && regno <= LAST_ALTIVEC_REGNO - 3);
+ }
+
+ else
+ return 0;
+ }
+
+ /* No other types other than XOmode can go in DMRs. */
+ if (DMR_REGNO_P (regno))
+ return 0;
/* PTImode can only go in GPRs. Quad word memory operations require even/odd
register combinations, and use PTImode where we need to deal with quad
@@ -2303,6 +2340,7 @@ rs6000_debug_reg_global (void)
rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
LAST_ALTIVEC_REGNO,
"vs");
+ rs6000_debug_reg_print (FIRST_DMR_REGNO, LAST_DMR_REGNO, "dmr");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
@@ -2323,6 +2361,7 @@ rs6000_debug_reg_global (void)
"wr reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
+ "wD reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
@@ -2330,7 +2369,8 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -2627,6 +2667,21 @@ rs6000_setup_reg_addr_masks (void)
addr_mask = 0;
reg = reload_reg_map[rc].reg;
+ /* Special case DMR registers. */
+ if (rc == RELOAD_REG_DMR)
+ {
+ if (TARGET_DENSE_MATH && m2 == XOmode)
+ {
+ addr_mask = RELOAD_REG_VALID;
+ reg_addr[m].addr_mask[rc] = addr_mask;
+ any_addr_mask |= addr_mask;
+ }
+ else
+ reg_addr[m].addr_mask[rc] = 0;
+
+ continue;
+ }
+
/* Can mode values go in the GPR/FPR/Altivec registers? */
if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
{
@@ -2781,6 +2836,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
rs6000_regno_regclass[r] = CR_REGS;
+ for (r = FIRST_DMR_REGNO; r <= LAST_DMR_REGNO; ++r)
+ rs6000_regno_regclass[r] = DM_REGS;
+
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
@@ -2805,6 +2863,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
+ reg_class_to_reg_type[(int)DM_REGS] = DMR_REG_TYPE;
if (TARGET_VSX)
{
@@ -2991,6 +3050,13 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
+ /* Support for the accumulator registers, either FPR registers (aka original
+ mma) or DMR registers (dense math). */
+ if (TARGET_DENSE_MATH)
+ rs6000_constraints[RS6000_CONSTRAINT_wD] = DM_REGS;
+ else if (TARGET_MMA)
+ rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;
+
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -4486,6 +4552,14 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
+ /* Dense math requires MMA. */
+ if (TARGET_DENSE_MATH && !TARGET_MMA)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0)
+ error ("%qs requires %qs", "-mdense-math", "-mmma");
+ rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH;
+ }
+
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -12379,6 +12453,11 @@ rs6000_secondary_reload_memory (rtx addr,
addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
& ~RELOAD_REG_AND_M16);
+ /* DMR registers use VSX registers, and need to generate some extra
+ instructions. */
+ else if (rclass == DM_REGS)
+ return 2;
+
/* If the register allocator hasn't made up its mind yet on the register
class to use, settle on defaults to use. */
else if (rclass == NO_REGS)
@@ -12707,6 +12786,13 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
|| (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
return true;
+ /* We can transfer between VSX registers and DMR registers without needing
+ extra registers. */
+ if (TARGET_DENSE_MATH && mode == XOmode
+ && ((to_type == DMR_REG_TYPE && from_type == VSX_REG_TYPE)
+ || (to_type == VSX_REG_TYPE && from_type == DMR_REG_TYPE)))
+ return true;
+
return false;
}
@@ -13401,6 +13487,10 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
machine_mode mode = GET_MODE (x);
bool is_constant = CONSTANT_P (x);
+ /* DMR registers can't be loaded or stored. */
+ if (rclass == DM_REGS)
+ return NO_REGS;
+
/* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
reload class for it. */
if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
@@ -13497,7 +13587,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
return VSX_REGS;
if (mode == XOmode)
- return FLOAT_REGS;
+ return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS;
if (GET_MODE_CLASS (mode) == MODE_INT)
return GENERAL_REGS;
@@ -13622,6 +13712,11 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
else
regno = -1;
+ /* DMR registers don't have loads or stores. We have to go through the VSX
+ registers to load XOmode (vector quad). */
+ if (TARGET_DENSE_MATH && rclass == DM_REGS)
+ return VSX_REGS;
+
/* If we have VSX register moves, prefer moving scalar values between
Altivec registers and GPR by going via an FPR (and then via memory)
instead of reloading the secondary memory address for Altivec moves. */
@@ -14135,8 +14230,14 @@ print_operand (FILE *file, rtx x, int code)
output_operand. */
case 'A':
- /* Write the MMA accumulator number associated with VSX register X. */
- if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
+ /* Write the MMA accumulator number associated with VSX register X. On
+ dense math systems, only allow DMR accumulators, not accumulators
+ overlapping with the FPR registers. */
+ if (!REG_P (x))
+ output_operand_lossage ("invalid %%A value");
+ else if (TARGET_DENSE_MATH && DMR_REGNO_P (REGNO (x)))
+ fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
+ else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
output_operand_lossage ("invalid %%A value");
else
fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4);
@@ -22789,6 +22890,31 @@ rs6000_debug_address_cost (rtx x, machine_mode mode,
}
+/* Subroutine to determine the move cost of dense math registers. If we are
+ moving to/from VSX_REGISTER registers, the cost is either 1 move (for
+ 512-bit accumulators) or 2 moves (for 1,024 dmr registers). If we are
+ moving to anything else like GPR registers, make the cost very high. */
+
+static int
+rs6000_dmr_register_move_cost (machine_mode mode, reg_class_t rclass)
+{
+ const int reg_move_base = 2;
+ HARD_REG_SET vsx_set = (reg_class_contents[rclass]
+ & reg_class_contents[VSX_REGS]);
+
+ if (TARGET_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))
+ {
+ /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */
+ if (mode == XOmode)
+ return reg_move_base;
+
+ else
+ return reg_move_base * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
+ }
+
+ return 1000 * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
+}
+
/* A C expression returning the cost of moving data from a register of class
CLASS1 to one of CLASS2. */
@@ -22802,17 +22928,28 @@ rs6000_register_move_cost (machine_mode mode,
if (TARGET_DEBUG_COST)
dbg_cost_ctrl++;
+ HARD_REG_SET to_vsx, from_vsx;
+ to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
+ from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
+
+ /* Special case DMR registers, that can only move to/from VSX registers. */
+ if (from == DM_REGS && to == DM_REGS)
+ ret = 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode);
+
+ else if (from == DM_REGS)
+ ret = rs6000_dmr_register_move_cost (mode, to);
+
+ else if (to == DM_REGS)
+ ret = rs6000_dmr_register_move_cost (mode, from);
+
/* If we have VSX, we can easily move between FPR or Altivec registers,
otherwise we can only easily move within classes.
Do this first so we give best-case answers for union classes
containing both gprs and vsx regs. */
- HARD_REG_SET to_vsx, from_vsx;
- to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
- from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
- if (!hard_reg_set_empty_p (to_vsx)
- && !hard_reg_set_empty_p (from_vsx)
- && (TARGET_VSX
- || hard_reg_set_intersect_p (to_vsx, from_vsx)))
+ else if (!hard_reg_set_empty_p (to_vsx)
+ && !hard_reg_set_empty_p (from_vsx)
+ && (TARGET_VSX
+ || hard_reg_set_intersect_p (to_vsx, from_vsx)))
{
int reg = FIRST_FPR_REGNO;
if (TARGET_VSX
@@ -22907,6 +23044,9 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
ret = 4 * hard_regno_nregs (32, mode);
else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
+ else if (reg_classes_intersect_p (rclass, DM_REGS))
+ ret = (rs6000_dmr_register_move_cost (mode, VSX_REGS)
+ + rs6000_memory_move_cost (mode, VSX_REGS, false));
else
ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
@@ -24115,6 +24255,8 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
if (TARGET_HARD_FLOAT)
pressure_classes[n++] = FLOAT_REGS;
}
+ if (TARGET_DENSE_MATH)
+ pressure_classes[n++] = DM_REGS;
pressure_classes[n++] = CR_REGS;
pressure_classes[n++] = SPECIAL_REGS;
@@ -24279,6 +24421,10 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format)
return 67;
if (regno == 64)
return 64;
+ /* XXX: This is a guess. The GCC register number for FIRST_DMR_REGNO is 111,
+ but the frame pointer regnum uses that. */
+ if (DMR_REGNO_P (regno))
+ return regno - FIRST_DMR_REGNO + 112;
gcc_unreachable ();
}
@@ -24489,6 +24635,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "crypto", OPTION_MASK_CRYPTO, false, true },
{ "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
{ "dlmzb", OPTION_MASK_DLMZB, false, true },
+ { "dense-math", OPTION_MASK_DENSE_MATH, false, true },
{ "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
false, true },
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
@@ -27575,7 +27722,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
|| XINT (src, 1) == UNSPECV_MMA_ASSEMBLE);
gcc_assert (REG_P (dst));
if (GET_MODE (src) == XOmode)
- gcc_assert (FP_REGNO_P (REGNO (dst)));
+ gcc_assert ((TARGET_DENSE_MATH
+ ? VSX_REGNO_P (REGNO (dst))
+ : FP_REGNO_P (REGNO (dst))));
if (GET_MODE (src) == OOmode)
gcc_assert (VSX_REGNO_P (REGNO (dst)));
@@ -662,6 +662,7 @@ extern unsigned char rs6000_recip_bits[];
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_VSX_WORD 16
+#define UNITS_PER_DMR_WORD 128
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -789,7 +790,7 @@ enum data_align { align_abi, align_opt, align_both };
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
pointer, which is eventually eliminated in favor of SP or FP. */
-#define FIRST_PSEUDO_REGISTER 111
+#define FIRST_PSEUDO_REGISTER 119
/* Use standard DWARF numbering for DWARF debugging information. */
#define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -826,7 +827,9 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* vrsave vscr sfp */ \
- 1, 1, 1 \
+ 1, 1, 1, \
+ /* DMR registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -850,7 +853,9 @@ enum data_align { align_abi, align_opt, align_both };
/* cr0..cr7 */ \
1, 1, 0, 0, 0, 1, 1, 1, \
/* vrsave vscr sfp */ \
- 0, 0, 0 \
+ 0, 0, 0, \
+ /* DMR registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -887,6 +892,7 @@ enum data_align { align_abi, align_opt, align_both };
v2 (not saved; incoming vector arg reg; return value)
v19 - v14 (not saved or used for anything)
v31 - v20 (saved; order given to save least number)
+ dmr0 - dmr7 (not saved)
vrsave, vscr (fixed)
sfp (fixed)
*/
@@ -929,6 +935,9 @@ enum data_align { align_abi, align_opt, align_both };
66, \
83, 82, 81, 80, 79, 78, \
95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
+ /* DMR registers. */ \
+ 111, 112, 113, 114, 115, 116, 117, 118, \
+ /* Vrsave, vscr, sfp. */ \
108, 109, \
110 \
}
@@ -955,6 +964,9 @@ enum data_align { align_abi, align_opt, align_both };
/* True if register is a VSX register. */
#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
+/* True if register is a DMR register. */
+#define DMR_REGNO_P(N) ((N) >= FIRST_DMR_REGNO && (N) <= LAST_DMR_REGNO)
+
/* Alternate name for any vector register supporting floating point, no matter
which instruction set(s) are available. */
#define VFLOAT_REGNO_P(N) \
@@ -1090,6 +1102,7 @@ enum reg_class
FLOAT_REGS,
ALTIVEC_REGS,
VSX_REGS,
+ DM_REGS,
VRSAVE_REGS,
VSCR_REGS,
GEN_OR_FLOAT_REGS,
@@ -1119,6 +1132,7 @@ enum reg_class
"FLOAT_REGS", \
"ALTIVEC_REGS", \
"VSX_REGS", \
+ "DM_REGS", \
"VRSAVE_REGS", \
"VSCR_REGS", \
"GEN_OR_FLOAT_REGS", \
@@ -1153,6 +1167,8 @@ enum reg_class
{ 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
/* VSX_REGS. */ \
{ 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
+ /* DM_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 }, \
/* VRSAVE_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
/* VSCR_REGS. */ \
@@ -1180,7 +1196,7 @@ enum reg_class
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff } \
}
/* The same information, inverted:
@@ -1204,6 +1220,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
+ RS6000_CONSTRAINT_wD, /* Accumulator regs if MMA/Dense Math. */
RS6000_CONSTRAINT_MAX
};
@@ -2077,7 +2094,16 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* vrsave */ \
&rs6000_reg_names[109][0], /* vscr */ \
\
- &rs6000_reg_names[110][0] /* sfp */ \
+ &rs6000_reg_names[110][0], /* sfp */ \
+ \
+ &rs6000_reg_names[111][0], /* dmr0 */ \
+ &rs6000_reg_names[112][0], /* dmr1 */ \
+ &rs6000_reg_names[113][0], /* dmr2 */ \
+ &rs6000_reg_names[114][0], /* dmr3 */ \
+ &rs6000_reg_names[115][0], /* dmr4 */ \
+ &rs6000_reg_names[116][0], /* dmr5 */ \
+ &rs6000_reg_names[117][0], /* dmr6 */ \
+ &rs6000_reg_names[118][0], /* dmr7 */ \
}
/* Table of additional register names to use in user input. */
@@ -2131,6 +2157,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
{"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
{"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
+ {"dmr0", 111}, {"dmr1", 112}, {"dmr2", 113}, {"dmr3", 114}, \
+ {"dmr4", 115}, {"dmr5", 116}, {"dmr6", 117}, {"dmr7", 118}, \
}
/* This is how to output an element of a case-vector that is relative. */
@@ -51,6 +51,8 @@ (define_constants
(VRSAVE_REGNO 108)
(VSCR_REGNO 109)
(FRAME_POINTER_REGNUM 110)
+ (FIRST_DMR_REGNO 111)
+ (LAST_DMR_REGNO 118)
])
;;
@@ -355,7 +357,7 @@ (define_attr "cpu"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dm,not_dm"
(const_string "any"))
;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -403,6 +405,14 @@ (define_attr "enabled" ""
(and (eq_attr "isa" "p10")
(match_test "TARGET_POWER10"))
(const_int 1)
+
+ (and (eq_attr "isa" "dm")
+ (match_test "TARGET_DENSE_MATH"))
+ (const_int 1)
+
+ (and (eq_attr "isa" "not_dm")
+ (match_test "!TARGET_DENSE_MATH"))
+ (const_int 1)
] (const_int 0)))
;; If this instruction is microcoded on the CELL processor
@@ -632,6 +632,10 @@ mfuture
Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags)
Generate (do not generate) future instructions.
+mdense-math
+Target Undocumented Mask(DENSE_MATH) Var(rs6000_isa_flags)
+Generate (do not generate) dense math instructions.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
@@ -3437,6 +3437,13 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}.
@item wA
Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.
+@item wD
+Accumulator register if @option{-mma} is used; otherwise,
+@code{NO_REGS}. If @option{-mdense-math} is used, the accumulator
+register will be in the dense match register set. If
+@option{-mno-dense-math} is used, the accumulator register will
+overlap with the VSX vector registers 0..31.
+
@item wB
Signed 5-bit constant integer that can be loaded into an Altivec register.