@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Guarded Control Stack (GCS) for AArch64.
+
* Add support for AArch64 Check Feature Status Extension (CHK).
* Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS.
@@ -10325,6 +10325,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"hbc", AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
{"cssc", AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES},
{"chk", AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES},
+ {"gcs", AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -261,6 +261,8 @@ automatically cause those extensions to be disabled.
@tab Enable Transactional Memory Extensions.
@item @code{chk} @tab ARMv8-A @tab No
@tab Enable Check Feature Status Extension.
+@item @code{gcs} @tab N/A @tab No
+ @tab Enable Guarded Control Stack Extension.
@end multitable
@node AArch64 Syntax
new file mode 100644
@@ -0,0 +1,3 @@
+#as: -march=armv9.2-a
+#source: gcs-1.s
+#error_output: gcs-1-bad.l
new file mode 100644
@@ -0,0 +1,45 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopcx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,sp'
new file mode 100644
@@ -0,0 +1,54 @@
+#name: Test of Guarded Control Stack Instructions.
+#as: -march=armv9.3-a+gcs
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: d508779f gcspushx
+.*: d50877bf gcspopcx
+.*: d50877df gcspopx
+.*: d52b773f gcspopm
+.*: d50b7700 gcspushm x0
+.*: d50b770f gcspushm x15
+.*: d50b771e gcspushm x30
+.*: d50b771f gcspushm xzr
+.*: d50b7740 gcsss1 x0
+.*: d50b774f gcsss1 x15
+.*: d50b775e gcsss1 x30
+.*: d50b775f gcsss1 xzr
+.*: d52b7760 gcsss2 x0
+.*: d52b776f gcsss2 x15
+.*: d52b777e gcsss2 x30
+.*: d52b777f gcsss2 xzr
+.*: d52b7720 gcspopm x0
+.*: d52b772f gcspopm x15
+.*: d52b773e gcspopm x30
+.*: d52b773f gcspopm
+.*: d91f0c20 gcsstr x0, x1
+.*: d91f0e00 gcsstr x0, x16
+.*: d91f0fe0 gcsstr x0, sp
+.*: d91f0c2f gcsstr x15, x1
+.*: d91f0e0f gcsstr x15, x16
+.*: d91f0fef gcsstr x15, sp
+.*: d91f0c3e gcsstr x30, x1
+.*: d91f0e1e gcsstr x30, x16
+.*: d91f0ffe gcsstr x30, sp
+.*: d91f0c3f gcsstr xzr, x1
+.*: d91f0e1f gcsstr xzr, x16
+.*: d91f0fff gcsstr xzr, sp
+.*: d91f1c20 gcssttr x0, x1
+.*: d91f1e00 gcssttr x0, x16
+.*: d91f1fe0 gcssttr x0, sp
+.*: d91f1c2f gcssttr x15, x1
+.*: d91f1e0f gcssttr x15, x16
+.*: d91f1fef gcssttr x15, sp
+.*: d91f1c3e gcssttr x30, x1
+.*: d91f1e1e gcssttr x30, x16
+.*: d91f1ffe gcssttr x30, sp
+.*: d91f1c3f gcssttr xzr, x1
+.*: d91f1e1f gcssttr xzr, x16
+.*: d91f1fff gcssttr xzr, sp
new file mode 100644
@@ -0,0 +1,19 @@
+ .text
+ gcspushx
+ gcspopcx
+ gcspopx
+ gcspopm
+
+ .irp op gcspushm, gcsss1, gcsss2, gcspopm
+ .irp reg1 x0, x15, x30, xzr
+ \op \reg1
+ .endr
+ .endr
+
+ .irp op gcsstr, gcssttr
+ .irp reg1 x0, x15, x30, xzr
+ .irp reg2 x1, x16, sp
+ \op \reg1, \reg2
+ .endr
+ .endr
+ .endr
@@ -161,6 +161,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_V8_9A,
/* Check Feature Status Extension. */
AARCH64_FEATURE_CHK,
+ /* Guarded Control Stack. */
+ AARCH64_FEATURE_GCS,
/* SME2. */
AARCH64_FEATURE_SME2,
DUMMY1,
@@ -897,6 +899,7 @@ enum aarch64_insn_class
dotproduct,
bfloat16,
cssc,
+ gcs,
};
/* Opcode enumerators. */
@@ -2574,6 +2574,8 @@ static const aarch64_feature_set aarch64_feature_cssc =
AARCH64_FEATURE (CSSC);
static const aarch64_feature_set aarch64_feature_chk =
AARCH64_FEATURE (CHK);
+static const aarch64_feature_set aarch64_feature_gcs =
+ AARCH64_FEATURE (GCS);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2633,6 +2635,7 @@ static const aarch64_feature_set aarch64_feature_chk =
#define HBC &aarch64_feature_hbc
#define CSSC &aarch64_feature_cssc
#define CHK &aarch64_feature_chk
+#define GCS &aarch64_feature_gcs
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2782,6 +2785,8 @@ static const aarch64_feature_set aarch64_feature_chk =
{ NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
{ NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
+ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -4141,6 +4146,16 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0),
+ GCS_INSN ("gcspushx", 0xd508779f, 0xffffffff, OP0 (), {}, 0),
+ GCS_INSN ("gcspopx", 0xd50877df, 0xffffffff, OP0 (), {}, 0),
+ GCS_INSN ("gcspopcx", 0xd50877bf, 0xffffffff, OP0 (), {}, 0),
+ GCS_INSN ("gcsss1", 0xd50b7740, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+ GCS_INSN ("gcspushm", 0xd50b7700, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+ GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+ GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0),
+ GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+ GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
+ GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),