diff mbox series

[1/4] RISC-V: Recategorize "prefetch" availabilities

Message ID e77808ffa394b3d5a322d4d1a83aca13004190cd.1698045769.git.research_trasio@irq.a4lg.com
State Unresolved
Headers
Series RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in) |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Tsukasa OI Oct. 23, 2023, 7:22 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

Because they are for all prefetch instructions, "prefetch" fits better
than "prefetchi".

gcc/ChangeLog:

	* config/riscv/riscv-builtins.cc: Rename availabilities
	"prefetchi{32,64}" to "prefetch{32,64}".
	* config/riscv/riscv-cmo.def
	(__builtin_riscv_zicbop_cbo_prefetchi):
	Reflect availability name changes.
---
 gcc/config/riscv/riscv-builtins.cc | 4 ++--
 gcc/config/riscv/riscv-cmo.def     | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

Comments

Jeff Law Oct. 30, 2023, 9:57 p.m. UTC | #1 
On 10/23/23 01:22, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> Because they are for all prefetch instructions, "prefetch" fits better
> than "prefetchi".
But there's  a significant difference between the cases.  prefetch.i in 
particular fetches into the icache.  While prefetch.r and prefetch.w 
would fetch into the data cache.

And I strongly suspect from an API standpoint we'll want to distinguish 
each case from the others.

Unless Kito feels otherwise I would suggest keeping a distinct API 
interface for each case.



Jeff
Kito Cheng Oct. 31, 2023, 1:17 a.m. UTC | #2 
> Unless Kito feels otherwise I would suggest keeping a distinct API
> interface for each case.

Yeah, I think they should have a distinct API.
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index fc3976f3ba12..ce549eb3782d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -103,8 +103,8 @@  AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
 AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
 AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
-AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
-AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (prefetch32, TARGET_ZICBOP && !TARGET_64BIT)
+AVAIL (prefetch64, TARGET_ZICBOP && TARGET_64BIT)
 AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
 AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
 AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index ff713b78e19e..017370d1d0e3 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -13,8 +13,8 @@  RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV
 RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, zero64),
 
 // zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetchi32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetchi64),
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI, prefetch32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_UDI_FTYPE_UDI, prefetch64),
 
 // zbkc or zbc
 RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),