diff mbox series

RISC-V: Make rv32i_zcmp testcase more robust

Message ID 20231030163701.1412946-1-patrick@rivosinc.com
State Unresolved
Headers
Series RISC-V: Make rv32i_zcmp testcase more robust |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Patrick O'Neill Oct. 30, 2023, 4:37 p.m. UTC 
  GCC recently changed its register allocator which causes this
testcase to fail.
This patch updates the regex to be more robust to change by accepting
any s register in the range of 1-9 for cm.push and cm.popret insns.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
	range of 1-9 for cm.push and cm.popret insns.
        
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
Tested using glibc rv64gc on r14-4980-g2672c60917d.
---
 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Jeff Law Oct. 30, 2023, 4:55 p.m. UTC | #1 
On 10/30/23 10:37, Patrick O'Neill wrote:
> GCC recently changed its register allocator which causes this
> testcase to fail.
> This patch updates the regex to be more robust to change by accepting
> any s register in the range of 1-9 for cm.push and cm.popret insns.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
> 	range of 1-9 for cm.push and cm.popret insns.
OK
jeff
Patrick O'Neill Oct. 30, 2023, 4:59 p.m. UTC | #2 
On 10/30/23 09:55, Jeff Law wrote:
>
>
> On 10/30/23 10:37, Patrick O'Neill wrote:
>> GCC recently changed its register allocator which causes this
>> testcase to fail.
>> This patch updates the regex to be more robust to change by accepting
>> any s register in the range of 1-9 for cm.push and cm.popret insns.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/rv32i_zcmp.c: Accept any register in the
>>     range of 1-9 for cm.push and cm.popret insns.
> OK
> jeff

Committed.

Patrick
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
index ea562b7a233..1e1a8be8705 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
@@ -26,9 +26,9 @@  f2 (void);
 /*
 **test1:
 **	...
-**	cm.push	{ra, s0-s4}, -80
+**	cm.push	{ra, s0-s[1-9]}, -80
 **	...
-**	cm.popret	{ra, s0-s4}, 80
+**	cm.popret	{ra, s0-s[1-9]}, 80
 **	...
 */
 int
@@ -50,9 +50,9 @@  test1 ()
 /*
 **test2_step1_0_size:
 **	...
-**	cm.push	{ra, s0-s1}, -64
+**	cm.push	{ra, s0-s[1-9]}, -64
 **	...
-**	cm.popret	{ra, s0-s1}, 64
+**	cm.popret	{ra, s0-s[1-9]}, 64
 **	...
 */
 int
@@ -70,9 +70,9 @@  test2_step1_0_size ()
 /*
 **test3:
 **	...
-**	cm.push	{ra, s0-s4}, -80
+**	cm.push	{ra, s0-s[1-9]}, -80
 **	...
-**	cm.popret	{ra, s0-s4}, 80
+**	cm.popret	{ra, s0-s[1-9]}, 80
 **	...
 */
 float