[1/2] arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes
Commit Message
Add USB host controller and PHY nodes.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 99 ++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
Comments
On 16/11/2022 14:22, Abel Vesa wrote:
> Add USB host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 99 ++++++++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..1b62395fe101 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1460,6 +1460,105 @@ opp-202000000 {
> };
> };
>
> + usb_1_hsphy: phy@88e3000 {
> + compatible = "qcom,sm8550-snps-eusb2-phy";
> + reg = <0x0 0x088e3000 0x0 0x154>;
> + status = "disabled";
Status last.
> + #phy-cells = <0>;
> +
> + clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1_qmpphy: phy-wrapper@88e9000 {
> + compatible = "qcom,sm8550-qmp-usb3-phy";
> + reg = <0x0 0x088e9000 0x0 0x200>,
> + <0x0 0x088e8000 0x0 0x20>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Move these four down, please.
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_PAD_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "ref_clk_src", "com_aux";
> +
> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_PHY_PRIM_BCR>;
Indentation seems off.
> + reset-names = "phy", "common";
> + power-domains = <&gcc USB3_PHY_GDSC>;
> +
> + usb_1_ssphy: phy@88e9200 {
> + reg = <0x0 0x088e9200 0x0 0x200>,
> + <0x0 0x088e9400 0x0 0x200>,
> + <0x0 0x088e9c00 0x0 0x400>,
> + <0x0 0x088e9600 0x0 0x200>,
> + <0x0 0x088e9800 0x0 0x200>,
> + <0x0 0x088e9a00 0x0 0x100>;
> + #phy-cells = <0>;
> + #clock-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
> + reg = <0x0 0x0a6f8800 0x0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Move these four down, please.
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&tcsr TCSR_USB3_CLKREF_EN>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 15 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 14 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "hs_phy_irq",
> + "ss_phy_irq",
> + "dm_hs_phy_irq",
> + "dp_hs_phy_irq";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x0a600000 0x0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x40 0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,usb3_lpm_capable;
> + phys = <&usb_1_ssphy>,
> + <&usb_1_hsphy>;
> + phy-names = "usb3-phy",
> + "usb2-phy";
No need for newlines here and in phys =
Konrad
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8550-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
On Wed, Nov 16, 2022 at 03:22:11PM +0200, Abel Vesa wrote:
> Add USB host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 99 ++++++++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 07ba709ca35f..1b62395fe101 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1460,6 +1460,105 @@ opp-202000000 {
> };
> };
>
> + usb_1_hsphy: phy@88e3000 {
> + compatible = "qcom,sm8550-snps-eusb2-phy";
> + reg = <0x0 0x088e3000 0x0 0x154>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1_qmpphy: phy-wrapper@88e9000 {
> + compatible = "qcom,sm8550-qmp-usb3-phy";
Where's the corresponding binding update?
> + reg = <0x0 0x088e9000 0x0 0x200>,
> + <0x0 0x088e8000 0x0 0x20>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_PAD_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "ref_clk_src", "com_aux";
Don't you have a dedicated ref clk? In any case, ref_clk_src should not
be here (either rename it 'ref' or replace it).
> +
> + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> + power-domains = <&gcc USB3_PHY_GDSC>;
> +
> + usb_1_ssphy: phy@88e9200 {
> + reg = <0x0 0x088e9200 0x0 0x200>,
> + <0x0 0x088e9400 0x0 0x200>,
> + <0x0 0x088e9c00 0x0 0x400>,
> + <0x0 0x088e9600 0x0 0x200>,
> + <0x0 0x088e9800 0x0 0x200>,
> + <0x0 0x088e9a00 0x0 0x100>;
> + #phy-cells = <0>;
> + #clock-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
As for UFS and PCIe these PHY nodes should be updated to use the new
binding scheme which drops the child node and individual register
descriptions (cf. sc8280xp).
> + };
Johan
@@ -1460,6 +1460,105 @@ opp-202000000 {
};
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e3000 0x0 0x154>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
+
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sm8550-qmp-usb3-phy";
+ reg = <0x0 0x088e9000 0x0 0x200>,
+ <0x0 0x088e8000 0x0 0x20>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_PAD_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "ref_clk_src", "com_aux";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+ power-domains = <&gcc USB3_PHY_GDSC>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0x0 0x088e9200 0x0 0x200>,
+ <0x0 0x088e9400 0x0 0x200>,
+ <0x0 0x088e9c00 0x0 0x400>,
+ <0x0 0x088e9600 0x0 0x200>,
+ <0x0 0x088e9800 0x0 0x200>,
+ <0x0 0x088e9a00 0x0 0x100>;
+ #phy-cells = <0>;
+ #clock-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a6f8800 0x0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&tcsr TCSR_USB3_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a600000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x40 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+ phys = <&usb_1_ssphy>,
+ <&usb_1_hsphy>;
+ phy-names = "usb3-phy",
+ "usb2-phy";
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8550-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;