Message ID | 20231027033104.1348921-2-chris.packham@alliedtelesis.co.nz |
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State | New |
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[23.128.96.35]) by mx.google.com with ESMTPS id 2-20020a250802000000b00d9cc997f223si1201999ybi.210.2023.10.26.20.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 20:31:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@alliedtelesis.co.nz header.s=mail181024 header.b=D0Wk1mvA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=alliedtelesis.co.nz Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id A18C582663AE; Thu, 26 Oct 2023 20:31:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345216AbjJ0DbS (ORCPT <rfc822;aposhian.dev@gmail.com> + 26 others); Thu, 26 Oct 2023 23:31:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234917AbjJ0DbQ (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 26 Oct 2023 23:31:16 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38806FA for <linux-kernel@vger.kernel.org>; Thu, 26 Oct 2023 20:31:12 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 24F412C011D; Fri, 27 Oct 2023 16:31:09 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1698377469; bh=fhjMiQeoXkVBPNXsIJuW1BQL7JD4RG68hd+jZlHsO3I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D0Wk1mvAYJdVtcq1ZERIFf/snAQK3ZiukPM8kD4lPZh/m9ZUyjPcD7UgDQu4ZUEBj qZ/exv/Wf8E0N4X0f/aQPFzN9Ce2Ke2ixjn/KuIcGS753dUAQIKiq9Bg5h/PsD2vW0 IIbg6WjFPkJ+pP08OjXKpV/Y2J0Ff2RlcvIxtg8ZRpBJQswx5vad+AUDQbmB4lWDVx kD11KuQpsbL/vSilQWZ6OikijiAUIcpY/lQKK1MBLTQz4P/tHKKAR2mFJx4t/9xqsP 3x+/d/3iAx1hVzwf8Q45zkZBkM+XHwN26irTZfisYMCnjkaJ/YmbLeEIqHlN3U31wx eH1Rk2Vcbavkw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id <B653b2efc0001>; Fri, 27 Oct 2023 16:31:08 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id 5E70413EE44; Fri, 27 Oct 2023 16:31:08 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 5A4F8280347; Fri, 27 Oct 2023 16:31:08 +1300 (NZDT) From: Chris Packham <chris.packham@alliedtelesis.co.nz> To: gregory.clement@bootlin.com, andi.shyti@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham <chris.packham@alliedtelesis.co.nz> Subject: [PATCH v5 1/2] dt-bindings: i2c: mv64xxx: add bus-reset-gpios property Date: Fri, 27 Oct 2023 16:31:03 +1300 Message-ID: <20231027033104.1348921-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231027033104.1348921-1-chris.packham@alliedtelesis.co.nz> References: <20231027033104.1348921-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=L6ZjvNb8 c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=bhdUkHdE2iEA:10 a=KKAkSRfTAAAA:8 a=N1qcaoclDu5WUfG3NQYA:9 a=cvBusfyB2V15izCimMoJ:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Thu, 26 Oct 2023 20:31:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780877895923456115 X-GMAIL-MSGID: 1780877895923456115 |
Series |
i2c: mv64xxx: bus-reset-gpios
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Commit Message
Chris Packham
Oct. 27, 2023, 3:31 a.m. UTC
Add bus-reset-gpios and bus-reset-duration-us properties to the marvell,mv64xxx-i2c binding. These can be used to describe hardware where a common reset GPIO is connected to all downstream devices on and I2C bus. This reset will be asserted then released before the downstream devices on the bus are probed. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Notes: Changes in v5: - Rename reset-gpios and reset-duration-us to bus-reset-gpios and bus-reset-duration-us as requested by Wolfram Changes in v4: - Add r-by from Krzysztof Changes in v3: - Rename reset-delay-us to reset-duration-us to better reflect its purpose - Add default: for reset-duration-us - Add description: for reset-gpios Changes in v2: - Update commit message - Add reset-delay-us property .../devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)
Comments
On Fri, Oct 27, 2023 at 04:31:03PM +1300, Chris Packham wrote: > Add bus-reset-gpios and bus-reset-duration-us properties to the > marvell,mv64xxx-i2c binding. These can be used to describe hardware > where a common reset GPIO is connected to all downstream devices on and > I2C bus. This reset will be asserted then released before the downstream > devices on the bus are probed. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Krzysztof, are you fine with this change? > --- > > Notes: > Changes in v5: > - Rename reset-gpios and reset-duration-us to bus-reset-gpios and > bus-reset-duration-us as requested by Wolfram > Changes in v4: > - Add r-by from Krzysztof > Changes in v3: > - Rename reset-delay-us to reset-duration-us to better reflect its > purpose > - Add default: for reset-duration-us > - Add description: for reset-gpios > Changes in v2: > - Update commit message > - Add reset-delay-us property > > .../devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > index 461d1c9ee3f7..b165d1c4f0b1 100644 > --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > @@ -70,6 +70,16 @@ properties: > resets: > maxItems: 1 > > + bus-reset-gpios: > + description: > + GPIO pin providing a common reset for all downstream devices. This GPIO > + will be asserted then released before the downstream devices are probed. > + maxItems: 1 > + > + bus-reset-duration-us: > + description: Reset duration in us. > + default: 1 > + > dmas: > items: > - description: RX DMA Channel > -- > 2.42.0 >
On 27/10/2023 11:09, Wolfram Sang wrote: > On Fri, Oct 27, 2023 at 04:31:03PM +1300, Chris Packham wrote: >> Add bus-reset-gpios and bus-reset-duration-us properties to the >> marvell,mv64xxx-i2c binding. These can be used to describe hardware >> where a common reset GPIO is connected to all downstream devices on and >> I2C bus. This reset will be asserted then released before the downstream >> devices on the bus are probed. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Krzysztof, are you fine with this change? Actually no. NAK. Not because of the naming, but because the new name triggered some new paths in my brain which brought the point - this is old problem of power sequencing of children. I believe this must be solved in more generic way. First - generic for all I2C devices. Second - generic also matching other buses/subsystems, which have similar problem. We did it for USB (onboard USB), MMC (unloved MMC power sequence) and now we are doing it for PCIe and few others (Cc: Abel) https://lpc.events/event/17/contributions/1507/ Current solution is heavily limited. What about regulators? What about buses having 2 reset lines (still the same bus)? What about sequence? Best regards, Krzysztof
On Fri, Oct 27, 2023 at 01:25:56PM +0200, Krzysztof Kozlowski wrote: > On 27/10/2023 11:09, Wolfram Sang wrote: > > On Fri, Oct 27, 2023 at 04:31:03PM +1300, Chris Packham wrote: > >> Add bus-reset-gpios and bus-reset-duration-us properties to the > >> marvell,mv64xxx-i2c binding. These can be used to describe hardware > >> where a common reset GPIO is connected to all downstream devices on and > >> I2C bus. This reset will be asserted then released before the downstream > >> devices on the bus are probed. > >> > >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > > > Krzysztof, are you fine with this change? > > Actually no. NAK. > > Not because of the naming, but because the new name triggered some new > paths in my brain which brought the point - this is old problem of power > sequencing of children. > > I believe this must be solved in more generic way. First - generic for > all I2C devices. Second - generic also matching other buses/subsystems, > which have similar problem. We did it for USB (onboard USB), MMC > (unloved MMC power sequence) and now we are doing it for PCIe and few > others (Cc: Abel) Unlike the others I2C doesn't expect to access the bus/device before devices probe, right? > https://lpc.events/event/17/contributions/1507/ Oh, good! > Current solution is heavily limited. What about regulators? What about > buses having 2 reset lines (still the same bus)? What about sequence? A more complicated case should be handled by the device's driver. If the GPIO reset was not shared we'd be handling it there too. I think what's needed is to solve the shared aspect. That's already done with reset subsys, so I think making 'reset-gpios' handled by it too is the way forward. That would handle the QCA WiFi/BT case I think. I'm not sure waiting for that or something else to happen is worth holding up this simple case. It's not the only case of a common reset for a bus (MDIO). Rob
On 27/10/2023 21:22, Rob Herring wrote: > On Fri, Oct 27, 2023 at 01:25:56PM +0200, Krzysztof Kozlowski wrote: >> On 27/10/2023 11:09, Wolfram Sang wrote: >>> On Fri, Oct 27, 2023 at 04:31:03PM +1300, Chris Packham wrote: >>>> Add bus-reset-gpios and bus-reset-duration-us properties to the >>>> marvell,mv64xxx-i2c binding. These can be used to describe hardware >>>> where a common reset GPIO is connected to all downstream devices on and >>>> I2C bus. This reset will be asserted then released before the downstream >>>> devices on the bus are probed. >>>> >>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >>> >>> Krzysztof, are you fine with this change? >> >> Actually no. NAK. >> >> Not because of the naming, but because the new name triggered some new >> paths in my brain which brought the point - this is old problem of power >> sequencing of children. >> >> I believe this must be solved in more generic way. First - generic for >> all I2C devices. Second - generic also matching other buses/subsystems, >> which have similar problem. We did it for USB (onboard USB), MMC >> (unloved MMC power sequence) and now we are doing it for PCIe and few >> others (Cc: Abel) > > Unlike the others I2C doesn't expect to access the bus/device before > devices probe, right? > >> https://lpc.events/event/17/contributions/1507/ > > Oh, good! > >> Current solution is heavily limited. What about regulators? What about >> buses having 2 reset lines (still the same bus)? What about sequence? > > A more complicated case should be handled by the device's driver. If the > GPIO reset was not shared we'd be handling it there too. I think what's > needed is to solve the shared aspect. That's already done with reset > subsys, so I think making 'reset-gpios' handled by it too is the way > forward. That would handle the QCA WiFi/BT case I think. > > I'm not sure waiting for that or something else to happen is worth > holding up this simple case. It's not the only case of a common reset > for a bus (MDIO). I argue also that this bus-reset-gpios is not a property of this I2C controller. IIUC, the I2C controller does not have a line to reset all children. It's the children who have reset lines and it happens it is shared. Just like my WSA884x case: https://lore.kernel.org/alsa-devel/84f9f1c4-0627-4986-8160-b4ab99469b81@linaro.org/ Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 461d1c9ee3f7..b165d1c4f0b1 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -70,6 +70,16 @@ properties: resets: maxItems: 1 + bus-reset-gpios: + description: + GPIO pin providing a common reset for all downstream devices. This GPIO + will be asserted then released before the downstream devices are probed. + maxItems: 1 + + bus-reset-duration-us: + description: Reset duration in us. + default: 1 + dmas: items: - description: RX DMA Channel