diff mbox series

[RFC] drm: bridge: samsung-dsim: Recalculate timings when rounding HFP up

Message ID 20231013031040.152282-1-aford173@gmail.com
State New
Headers
Series [RFC] drm: bridge: samsung-dsim: Recalculate timings when rounding HFP up |

Commit Message

Adam Ford Oct. 13, 2023, 3:10 a.m. UTC 
  When using video sync pulses, the HFP, HBP, and HSA are divided between
the available lanes if there is more than one lane.  For certain
timings and lane configurations, the HFP may not be evenly divisible
and it gets rounded down which can cause certain resolutions and
refresh rates to not sync.

ie. 720p60 on some monitors show hss of 1390 and hdisplay of 1280.  This
yields an HFP of 110. When taking the HFP of 110 divides along 4 lanes,
the result is 27.5 which rounds down to 27 and causes some monitors not
to sync.

The solultion is to round HFP up by finding the remainder of HFP /
the number of lanes and increasing the hsync_start, hsync_end, and
htotal to compensate when there is a remainder.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
This adds support for 720p60 in the i.MX8M Plus.

NXP uses a look-up table in their downstream code to accomplish this.
Using this calculation, the driver can adjust without the need for a
complicated table and should be flexible for different timings and
resolutions depending on the monitor.

I don't have a DSI analyzer, and this appears to only work on
i.MX8M Plus but not Mini and Nano for some reason, despite their
having a similar DSI bridge.

Comments

Frieder Schrempf Oct. 26, 2023, 6:12 p.m. UTC | #1 
Hi Adam,

On 13.10.23 05:10, Adam Ford wrote:
> When using video sync pulses, the HFP, HBP, and HSA are divided between
> the available lanes if there is more than one lane.  For certain
> timings and lane configurations, the HFP may not be evenly divisible
> and it gets rounded down which can cause certain resolutions and
> refresh rates to not sync.
> 
> ie. 720p60 on some monitors show hss of 1390 and hdisplay of 1280.  This
> yields an HFP of 110. When taking the HFP of 110 divides along 4 lanes,
> the result is 27.5 which rounds down to 27 and causes some monitors not
> to sync.
> 
> The solultion is to round HFP up by finding the remainder of HFP /
> the number of lanes and increasing the hsync_start, hsync_end, and
> htotal to compensate when there is a remainder.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
> This adds support for 720p60 in the i.MX8M Plus.
> 
> NXP uses a look-up table in their downstream code to accomplish this.
> Using this calculation, the driver can adjust without the need for a
> complicated table and should be flexible for different timings and
> resolutions depending on the monitor.
> 
> I don't have a DSI analyzer, and this appears to only work on
> i.MX8M Plus but not Mini and Nano for some reason, despite their
> having a similar DSI bridge.

I just want to report that I have tested this patch (on top of current
linux-next) on our Kontron BL i.MX8MM board with the ADV7535 bridge and
I don't see any change when trying the 30 different modes the monitor
reports as supported. 18 of those work and 12 don't work.

So at least there is no negative impact in this case.

Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL
i.MX8MM with HDMI monitor

Thanks
Frieder
Adam Ford Oct. 26, 2023, 6:23 p.m. UTC | #2 
On Thu, Oct 26, 2023 at 1:12 PM Frieder Schrempf
<frieder.schrempf@kontron.de> wrote:
>
> Hi Adam,
>
> On 13.10.23 05:10, Adam Ford wrote:
> > When using video sync pulses, the HFP, HBP, and HSA are divided between
> > the available lanes if there is more than one lane.  For certain
> > timings and lane configurations, the HFP may not be evenly divisible
> > and it gets rounded down which can cause certain resolutions and
> > refresh rates to not sync.
> >
> > ie. 720p60 on some monitors show hss of 1390 and hdisplay of 1280.  This
> > yields an HFP of 110. When taking the HFP of 110 divides along 4 lanes,
> > the result is 27.5 which rounds down to 27 and causes some monitors not
> > to sync.
> >
> > The solultion is to round HFP up by finding the remainder of HFP /
> > the number of lanes and increasing the hsync_start, hsync_end, and
> > htotal to compensate when there is a remainder.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > ---
> > This adds support for 720p60 in the i.MX8M Plus.
> >
> > NXP uses a look-up table in their downstream code to accomplish this.
> > Using this calculation, the driver can adjust without the need for a
> > complicated table and should be flexible for different timings and
> > resolutions depending on the monitor.
> >
> > I don't have a DSI analyzer, and this appears to only work on
> > i.MX8M Plus but not Mini and Nano for some reason, despite their
> > having a similar DSI bridge.
>
> I just want to report that I have tested this patch (on top of current
> linux-next) on our Kontron BL i.MX8MM board with the ADV7535 bridge and
> I don't see any change when trying the 30 different modes the monitor
> reports as supported. 18 of those work and 12 don't work.

Thanks for testing this.   I didn't see any regressions on my Mini or
Nano either, but I did see the 720p60 now works on i.MX8M Plus (but
not on Mini/Nano).  I am not sure why, and I don't have a DSI
analyzer.

>
> So at least there is no negative impact in this case.

At least nothing broke.  :-)

>
> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL
> i.MX8MM with HDMI monitor

I'll add your T-b when I post it again.
>
> Thanks
> Frieder
diff mbox series

Patch

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index be5914caa17d..5564e85f6b63 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1628,6 +1628,26 @@  static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
 		adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 	}
 
+	/*
+	 * When using video sync pulses, the HFP, HBP, and HSA are divided between
+	 * the available lanes if there is more than one lane.  For certain
+	 * timings and lane configurations, the HFP may not be evenly divisible.
+	 * This can cause HFP to round down, and it ends up being too small which can
+	 * cause some monitors to not sync properly. In these instances, round HFP up
+	 * and adjust htotal to compensate. Through trial and error, it appears that
+	 * the HBP and HSA do not appear to need the same correction that HFP does.
+	 */
+	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE && dsi->lanes > 1) {
+		int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
+		int remainder = hfp % dsi->lanes;
+
+		if (remainder) {
+			adjusted_mode->hsync_start += remainder;
+			adjusted_mode->hsync_end   += remainder;
+			adjusted_mode->htotal      += remainder;
+		}
+	}
+
 	return 0;
 }