diff mbox series

RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]

Message ID 202310241422412928693@eswincomputing.com
State Not Applicable
Headers
Series RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935] |

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Context Check Description
snail/gcc-patch-check fail Git am fail log

Commit Message

Li Xu Oct. 24, 2023, 6:22 a.m. UTC 
  Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.

PR target/111935
gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Don't use the e.target directly.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vget_vset.c: New test.
---
 .../riscv/riscv-vector-builtins-bases.cc      | 13 ++--
 .../gcc.target/riscv/rvv/base/vget_vset.c     | 74 +++++++++++++++++++
 2 files changed, 81 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c

-- 
2.17.1




xuli1@eswincomputing.com

Comments

juzhe.zhong@rivai.ai Oct. 24, 2023, 6:47 a.m. UTC | #1 
Thanks for investigating it.

I think it's more reasonable to early return when e.target is NULL_RTX:

    if (!e.target)
      return NULL_RTX;

instead of change the current codes.

And

Could you add test pr111935.c with the PR code:

#include "riscv_vector.h"

inline vuint32m4_t __attribute__((__always_inline__)) transpose_indexes() {
  static const uint32_t idx_[16] = {0, 4, 8, 12,
                      1, 5, 9, 13,
                      2, 6, 10, 14,
                      3, 7, 11, 15};
  return __riscv_vle32_v_u32m4(idx_, 16);
}
void pffft_real_preprocess_4x4(const float *in) {
  vfloat32m1_t r0=__riscv_vle32_v_f32m1(in,4);
  vfloat32m4_t tmp = __riscv_vundefined_f32m4();
  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 0, r0);
  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 1, r0);
  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 2, r0);
  tmp = __riscv_vset_v_f32m1_f32m4(tmp, 3, r0);
  tmp = __riscv_vrgather_vv_f32m4(tmp, transpose_indexes(), 16);
  r0 = __riscv_vget_v_f32m4_f32m1(tmp, 0);
}





juzhe.zhong@rivai.ai
 
From: Li Xu
Date: 2023-10-24 14:22
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: RISC-V: Fix ICE of RVV vget/vset intrinsic[PR111935]
Calling vget/vset intrinsic without receiving a return value will cause
a crash. Because in this case e.target is null.
This patch should be backported to releases/gcc-13.

PR target/111935
gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Don't use the e.target directly.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vget_vset.c: New test.
---
 .../riscv/riscv-vector-builtins-bases.cc      | 13 ++--
 .../gcc.target/riscv/rvv/base/vget_vset.c     | 74 +++++++++++++++++++
 2 files changed, 81 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ab12e130907..4c9209bec6d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1745,11 +1745,12 @@ public:
     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 2));
     poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (src));
-    emit_move_insn (e.target, dest);
-    rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target,
-       GET_MODE (e.target), offset);
+    rtx ret = gen_reg_rtx (GET_MODE (dest));
+    emit_move_insn (ret, dest);
+    rtx subreg = simplify_gen_subreg (GET_MODE (src), ret,
+       GET_MODE (ret), offset);
     emit_move_insn (subreg, src);
-    return e.target;
+    return ret;
   }
 };
 
@@ -1780,9 +1781,9 @@ public:
     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
     gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
-    poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (e.target));
+    poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (e.ret_mode ());
     rtx subreg
-      = simplify_gen_subreg (GET_MODE (e.target), src, GET_MODE (src), offset);
+      = simplify_gen_subreg (e.ret_mode (), src, GET_MODE (src), offset);
     return subreg;
   }
 };
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
new file mode 100644
index 00000000000..e0d03871a64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
@@ -0,0 +1,74 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O0 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+void test_vget_v_f16m8_f16m1(vfloat16m8_t src, size_t index) {
+  __riscv_vget_v_f16m8_f16m1(src, 0);
+}
+
+void test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) {
+  __riscv_vget_v_f32m4_f32m1(src, 0);
+}
+
+void test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) {
+  __riscv_vget_v_f64m2_f64m1(src, 0);
+}
+
+void test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) {
+  __riscv_vget_v_i8m4_i8m1(src, 0);
+}
+
+void test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) {
+  __riscv_vget_v_i16m2_i16m1(src, 0);
+}
+
+void test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) {
+  __riscv_vget_v_i32m4_i32m1(src, 0);
+}
+
+void test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) {
+  __riscv_vget_v_i64m4_i64m1(src, 0);
+}
+
+void test_vset_v_f16m1_f16m4(vfloat16m4_t dest, size_t index,
+                                     vfloat16m1_t value) {
+  __riscv_vset_v_f16m1_f16m4(dest, 0, value);
+}
+
+void test_vset_v_f32m1_f32m2(vfloat32m2_t dest, size_t index,
+                                     vfloat32m1_t value) {
+  __riscv_vset_v_f32m1_f32m2(dest, 0, value);
+}
+
+void test_vset_v_f64m1_f64m4(vfloat64m4_t dest, size_t index,
+                                     vfloat64m1_t value) {
+  __riscv_vset_v_f64m1_f64m4(dest, 0, value);
+}
+
+void test_vset_v_i8m1_i8m4(vint8m4_t dest, size_t index, vint8m1_t value) {
+  __riscv_vset_v_i8m1_i8m4(dest, 0, value);
+}
+
+void test_vset_v_i16m1_i16m2(vint16m2_t dest, size_t index,
+                                   vint16m1_t value) {
+  __riscv_vset_v_i16m1_i16m2(dest, 0, value);
+}
+
+void test_vset_v_i32m1_i32m4(vint32m4_t dest, size_t index,
+                                   vint32m1_t value) {
+  __riscv_vset_v_i32m1_i32m4(dest, 0, value);
+}
+
+void test_vset_v_i64m1_i64m2(vint64m2_t dest, size_t index,
+                                   vint64m1_t value) {
+  __riscv_vset_v_i64m1_i64m2(dest, 0, value);
+}
+
+/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 27 } } */
+/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 21 } } */
-- 
2.17.1




xuli1@eswincomputing.com
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ab12e130907..4c9209bec6d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1745,11 +1745,12 @@  public:
     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 2));
     poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (src));
-    emit_move_insn (e.target, dest);
-    rtx subreg = simplify_gen_subreg (GET_MODE (src), e.target,
-       GET_MODE (e.target), offset);
+    rtx ret = gen_reg_rtx (GET_MODE (dest));
+    emit_move_insn (ret, dest);
+    rtx subreg = simplify_gen_subreg (GET_MODE (src), ret,
+       GET_MODE (ret), offset);
     emit_move_insn (subreg, src);
-    return e.target;
+    return ret;
   }
 };
 
@@ -1780,9 +1781,9 @@  public:
     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
     gcc_assert (riscv_v_ext_vector_mode_p (GET_MODE (src)));
     rtx index = expand_normal (CALL_EXPR_ARG (e.exp, 1));
-    poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (GET_MODE (e.target));
+    poly_int64 offset = INTVAL (index) * GET_MODE_SIZE (e.ret_mode ());
     rtx subreg
-      = simplify_gen_subreg (GET_MODE (e.target), src, GET_MODE (src), offset);
+      = simplify_gen_subreg (e.ret_mode (), src, GET_MODE (src), offset);
     return subreg;
   }
 };
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
new file mode 100644
index 00000000000..e0d03871a64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vget_vset.c
@@ -0,0 +1,74 @@ 
+
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O0 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+typedef float float32_t;
+typedef double float64_t;
+
+void test_vget_v_f16m8_f16m1(vfloat16m8_t src, size_t index) {
+  __riscv_vget_v_f16m8_f16m1(src, 0);
+}
+
+void test_vget_v_f32m4_f32m1(vfloat32m4_t src, size_t index) {
+  __riscv_vget_v_f32m4_f32m1(src, 0);
+}
+
+void test_vget_v_f64m2_f64m1(vfloat64m2_t src, size_t index) {
+  __riscv_vget_v_f64m2_f64m1(src, 0);
+}
+
+void test_vget_v_i8m4_i8m1(vint8m4_t src, size_t index) {
+  __riscv_vget_v_i8m4_i8m1(src, 0);
+}
+
+void test_vget_v_i16m2_i16m1(vint16m2_t src, size_t index) {
+  __riscv_vget_v_i16m2_i16m1(src, 0);
+}
+
+void test_vget_v_i32m4_i32m1(vint32m4_t src, size_t index) {
+  __riscv_vget_v_i32m4_i32m1(src, 0);
+}
+
+void test_vget_v_i64m4_i64m1(vint64m4_t src, size_t index) {
+  __riscv_vget_v_i64m4_i64m1(src, 0);
+}
+
+void test_vset_v_f16m1_f16m4(vfloat16m4_t dest, size_t index,
+                                     vfloat16m1_t value) {
+  __riscv_vset_v_f16m1_f16m4(dest, 0, value);
+}
+
+void test_vset_v_f32m1_f32m2(vfloat32m2_t dest, size_t index,
+                                     vfloat32m1_t value) {
+  __riscv_vset_v_f32m1_f32m2(dest, 0, value);
+}
+
+void test_vset_v_f64m1_f64m4(vfloat64m4_t dest, size_t index,
+                                     vfloat64m1_t value) {
+  __riscv_vset_v_f64m1_f64m4(dest, 0, value);
+}
+
+void test_vset_v_i8m1_i8m4(vint8m4_t dest, size_t index, vint8m1_t value) {
+  __riscv_vset_v_i8m1_i8m4(dest, 0, value);
+}
+
+void test_vset_v_i16m1_i16m2(vint16m2_t dest, size_t index,
+                                   vint16m1_t value) {
+  __riscv_vset_v_i16m1_i16m2(dest, 0, value);
+}
+
+void test_vset_v_i32m1_i32m4(vint32m4_t dest, size_t index,
+                                   vint32m1_t value) {
+  __riscv_vset_v_i32m1_i32m4(dest, 0, value);
+}
+
+void test_vset_v_i64m1_i64m2(vint64m2_t dest, size_t index,
+                                   vint64m1_t value) {
+  __riscv_vset_v_i64m1_i64m2(dest, 0, value);
+}
+
+/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 27 } } */
+/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-z]+[0-9]+\)} 21 } } */