diff mbox series

[V2,3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes

Message ID 20231019060651.23341-4-praveen.teja.kundanala@amd.com
State New
Headers
Series Add ZynqMP efuse access support |

Commit Message

Praveen Teja Kundanala Oct. 19, 2023, 6:06 a.m. UTC 
  Add nvmem DT nodes for ZynqMP SOC

Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Oct. 19, 2023, 9:27 a.m. UTC | #1 
On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> Add nvmem DT nodes for ZynqMP SOC
> 
> Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> ---
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++++++++++++++-
>  1 file changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index b61fc99cd911..b7433e6b9d6c 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
>  				mbox-names = "tx", "rx";
>  			};
>  
> -			nvmem_firmware {
> +			nvmem-firmware {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation


>  				compatible = "xlnx,zynqmp-nvmem-fw";

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).

>  				#address-cells = <1>;
>  				#size-cells = <1>;
>  
> -				soc_revision: soc_revision@0 {
> +				soc_revision: soc-revision@0 {
>  					reg = <0x0 0x4>;
>  				};

Wasn't this fixed already by Michal?


Best regards,
Krzysztof
Praveen Teja Kundanala Oct. 19, 2023, 10:32 a.m. UTC | #2 
[AMD Official Use Only - General]

Hi Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Thursday, October 19, 2023 2:58 PM
> To: Kundanala, Praveen Teja <praveen.teja.kundanala@amd.com>;
> srinivas.kandagatla@linaro.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; Simek, Michal
> <michal.simek@amd.com>; Kundanala, Praveen Teja
> <praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Subject: Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
> > Add nvmem DT nodes for ZynqMP SOC
> >
> > Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
> > ---
> >  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59
> > +++++++++++++++++++++++++-
> >  1 file changed, 57 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > index b61fc99cd911..b7433e6b9d6c 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> > @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
> >                               mbox-names = "tx", "rx";
> >                       };
> >
> > -                     nvmem_firmware {
> > +                     nvmem-firmware {
>
> Node names should be generic. See also an explanation and list of examples
> (not exhaustive) in DT specification:
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-
> basics.html#generic-names-recommendation
[Kundanala, Praveen Teja] Okay
>
>
> >                               compatible = "xlnx,zynqmp-nvmem-fw";
>
> It does not look like you tested the DTS against bindings. Please run `make
> dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst
> or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-
> sources-with-the-devicetree-schema/
> for instructions).
[Kundanala, Praveen Teja] Missed it, Will run and send V3.
>
> >                               #address-cells = <1>;
> >                               #size-cells = <1>;
> >
> > -                             soc_revision: soc_revision@0 {
> > +                             soc_revision: soc-revision@0 {
> >                                       reg = <0x0 0x4>;
> >                               };
>
> Wasn't this fixed already by Michal?
[Kundanala, Praveen Teja] Took base on Srinivas for-next repo and Michal's changes were not reflected in that repo.
>
>
> Best regards,
> Krzysztof
Michal Simek Oct. 20, 2023, 7:23 a.m. UTC | #3 
Hi,

On 10/19/23 12:32, Kundanala, Praveen Teja wrote:
> [AMD Official Use Only - General]
> 
> Hi Kozlowski,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Sent: Thursday, October 19, 2023 2:58 PM
>> To: Kundanala, Praveen Teja <praveen.teja.kundanala@amd.com>;
>> srinivas.kandagatla@linaro.org; robh+dt@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; Simek, Michal
>> <michal.simek@amd.com>; Kundanala, Praveen Teja
>> <praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes
>>
>> Caution: This message originated from an External Source. Use proper caution
>> when opening attachments, clicking links, or responding.
>>
>>
>> On 19/10/2023 08:06, Praveen Teja Kundanala wrote:
>>> Add nvmem DT nodes for ZynqMP SOC
>>>
>>> Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
>>> ---
>>>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59
>>> +++++++++++++++++++++++++-
>>>   1 file changed, 57 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> index b61fc99cd911..b7433e6b9d6c 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>> @@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
>>>                                mbox-names = "tx", "rx";
>>>                        };
>>>
>>> -                     nvmem_firmware {
>>> +                     nvmem-firmware {
>>
>> Node names should be generic. See also an explanation and list of examples
>> (not exhaustive) in DT specification:
>> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-
>> basics.html#generic-names-recommendation
> [Kundanala, Praveen Teja] Okay
>>
>>
>>>                                compatible = "xlnx,zynqmp-nvmem-fw";
>>
>> It does not look like you tested the DTS against bindings. Please run `make
>> dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst
>> or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-
>> sources-with-the-devicetree-schema/
>> for instructions).
> [Kundanala, Praveen Teja] Missed it, Will run and send V3.
>>
>>>                                #address-cells = <1>;
>>>                                #size-cells = <1>;
>>>
>>> -                             soc_revision: soc_revision@0 {
>>> +                             soc_revision: soc-revision@0 {
>>>                                        reg = <0x0 0x4>;
>>>                                };
>>
>> Wasn't this fixed already by Michal?
> [Kundanala, Praveen Teja] Took base on Srinivas for-next repo and Michal's changes were not reflected in that repo.

Feel free to drop this from series that it can go via nvmem tree directly.
And when this is merged we can add just this patch via my tree.

Thanks,
Michal
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b61fc99cd911..b7433e6b9d6c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -194,14 +194,69 @@  zynqmp_power: zynqmp-power {
 				mbox-names = "tx", "rx";
 			};
 
-			nvmem_firmware {
+			nvmem-firmware {
 				compatible = "xlnx,zynqmp-nvmem-fw";
 				#address-cells = <1>;
 				#size-cells = <1>;
 
-				soc_revision: soc_revision@0 {
+				soc_revision: soc-revision@0 {
 					reg = <0x0 0x4>;
 				};
+				/* efuse access */
+				efuse_dna: efuse-dna@c {
+					reg = <0xc 0xc>;
+				};
+				efuse_usr0: efuse-usr0@20 {
+					reg = <0x20 0x4>;
+				};
+				efuse_usr1: efuse-usr1@24 {
+					reg = <0x24 0x4>;
+				};
+				efuse_usr2: efuse-usr2@28 {
+					reg = <0x28 0x4>;
+				};
+				efuse_usr3: efuse-usr3@2c {
+					reg = <0x2c 0x4>;
+				};
+				efuse_usr4: efuse-usr4@30 {
+					reg = <0x30 0x4>;
+				};
+				efuse_usr5: efuse-usr5@34 {
+					reg = <0x34 0x4>;
+				};
+				efuse_usr6: efuse-usr6@38 {
+					reg = <0x38 0x4>;
+				};
+				efuse_usr7: efuse-usr7@3c {
+					reg = <0x3c 0x4>;
+				};
+				efuse_miscusr: efuse-miscusr@40 {
+					reg = <0x40 0x4>;
+				};
+				efuse_chash: efuse-chash@50 {
+					reg = <0x50 0x4>;
+				};
+				efuse_pufmisc: efuse-pufmisc@54 {
+					reg = <0x54 0x4>;
+				};
+				efuse_sec: efuse-sec@58 {
+					reg = <0x58 0x4>;
+				};
+				efuse_spkid: efuse-spkid@5c {
+					reg = <0x5c 0x4>;
+				};
+				efuse_aeskey: efuse-aeskey@60 {
+					reg = <0x60 0x20>;
+				};
+				efuse_ppk0hash: efuse-ppk0hash@a0 {
+					reg = <0xa0 0x30>;
+				};
+				efuse_ppk1hash: efuse-ppk1hash@d0 {
+					reg = <0xd0 0x30>;
+				};
+				efuse_pufuser: efuse-pufuser@100 {
+					reg = <0x100 0x7F>;
+				};
 			};
 
 			zynqmp_pcap: pcap {