Message ID | 20231011111438.909552-2-cleger@rivosinc.com |
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State | New |
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([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:14 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org> Subject: [PATCH v1 01/13] riscv: fatorize hwprobe ISA extension reporting Date: Wed, 11 Oct 2023 13:14:26 +0200 Message-ID: <20231011111438.909552-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=2.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SBL_CSS, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 11 Oct 2023 04:19:52 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779457793534002346 X-GMAIL-MSGID: 1779457793534002346 |
Series |
riscv: report more ISA extensions through hwprobe
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Commit Message
Clément Léger
Oct. 11, 2023, 11:14 a.m. UTC
Factorize ISA extension reporting by using a macro rather than
copy/pasting extension names. This will allow adding new extensions more
easily.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
Comments
correct misspelling of "fatorize" in subject line rday
Drew, On Wed, Oct 11, 2023 at 01:14:26PM +0200, Clément Léger wrote: > Factorize ISA extension reporting by using a macro rather than > copy/pasting extension names. This will allow adding new extensions more > easily. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++-------------- > 1 file changed, 12 insertions(+), 14 deletions(-) > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > index 473159b5f303..5ce593ce07a4 100644 > --- a/arch/riscv/kernel/sys_riscv.c > +++ b/arch/riscv/kernel/sys_riscv.c > @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > for_each_cpu(cpu, cpus) { We were gonna add a comment here about when it is and is not safe to use riscv_isa_extension_available() IIRC. Did that ever end up in a patch? > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > > - if (riscv_isa_extension_available(isainfo->isa, ZBA)) > - pair->value |= RISCV_HWPROBE_EXT_ZBA; > - else > - missing |= RISCV_HWPROBE_EXT_ZBA; > - > - if (riscv_isa_extension_available(isainfo->isa, ZBB)) > - pair->value |= RISCV_HWPROBE_EXT_ZBB; > - else > - missing |= RISCV_HWPROBE_EXT_ZBB; > - > - if (riscv_isa_extension_available(isainfo->isa, ZBS)) > - pair->value |= RISCV_HWPROBE_EXT_ZBS; > - else > - missing |= RISCV_HWPROBE_EXT_ZBS; > +#define CHECK_ISA_EXT(__ext) \ > + do { \ > + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ > + pair->value |= RISCV_HWPROBE_EXT_##__ext; \ > + else \ > + missing |= RISCV_HWPROBE_EXT_##__ext; \ > + } while (false) \ > + > + CHECK_ISA_EXT(ZBA); > + CHECK_ISA_EXT(ZBB); > + CHECK_ISA_EXT(ZBS); > +#undef CHECK_ISA_EXT > } > > /* Now turn off reporting features if any CPU is missing it. */ > -- > 2.42.0 >
On Thu, Oct 12, 2023 at 02:53:43PM +0100, Conor Dooley wrote: > Drew, > > On Wed, Oct 11, 2023 at 01:14:26PM +0200, Clément Léger wrote: > > Factorize ISA extension reporting by using a macro rather than > > copy/pasting extension names. This will allow adding new extensions more > > easily. > > > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > > --- > > arch/riscv/kernel/sys_riscv.c | 26 ++++++++++++-------------- > > 1 file changed, 12 insertions(+), 14 deletions(-) > > > > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c > > index 473159b5f303..5ce593ce07a4 100644 > > --- a/arch/riscv/kernel/sys_riscv.c > > +++ b/arch/riscv/kernel/sys_riscv.c > > @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > for_each_cpu(cpu, cpus) { > > We were gonna add a comment here about when it is and is not safe to use > riscv_isa_extension_available() IIRC. Did that ever end up in a patch? Yup, it's in [1]. But that series may be hung up on spec stuff, so maybe it'd be better for Clément to integrate it. And, it appears we definitely need this macro, because it has now been suggested by three different people :-) (I later saw Samuel was first[2], but I hadn't seen his before submitting mine, otherwise I would have given him the credit.) [1] https://lore.kernel.org/all/20230918131518.56803-11-ajones@ventanamicro.com/ [2] https://lore.kernel.org/all/20230712084134.1648008-4-sameo@rivosinc.com/ Thanks, drew > > > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > > > > - if (riscv_isa_extension_available(isainfo->isa, ZBA)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBA; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBA; > > - > > - if (riscv_isa_extension_available(isainfo->isa, ZBB)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBB; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBB; > > - > > - if (riscv_isa_extension_available(isainfo->isa, ZBS)) > > - pair->value |= RISCV_HWPROBE_EXT_ZBS; > > - else > > - missing |= RISCV_HWPROBE_EXT_ZBS; > > +#define CHECK_ISA_EXT(__ext) \ > > + do { \ > > + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ > > + pair->value |= RISCV_HWPROBE_EXT_##__ext; \ > > + else \ > > + missing |= RISCV_HWPROBE_EXT_##__ext; \ > > + } while (false) \ > > + > > + CHECK_ISA_EXT(ZBA); > > + CHECK_ISA_EXT(ZBB); > > + CHECK_ISA_EXT(ZBS); > > +#undef CHECK_ISA_EXT > > } > > > > /* Now turn off reporting features if any CPU is missing it. */ > > -- > > 2.42.0 > >
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 473159b5f303..5ce593ce07a4 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,18 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo = &hart_isa[cpu]; - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |= RISCV_HWPROBE_EXT_ZBA; - else - missing |= RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |= RISCV_HWPROBE_EXT_ZBB; - else - missing |= RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |= RISCV_HWPROBE_EXT_ZBS; - else - missing |= RISCV_HWPROBE_EXT_ZBS; +#define CHECK_ISA_EXT(__ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, __ext)) \ + pair->value |= RISCV_HWPROBE_EXT_##__ext; \ + else \ + missing |= RISCV_HWPROBE_EXT_##__ext; \ + } while (false) \ + + CHECK_ISA_EXT(ZBA); + CHECK_ISA_EXT(ZBB); + CHECK_ISA_EXT(ZBS); +#undef CHECK_ISA_EXT } /* Now turn off reporting features if any CPU is missing it. */