Message ID | 20221115133105.980877-7-robert.foss@linaro.org |
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State | New |
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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id q22-20020aa7d456000000b004618f2127d2sm6162176edr.57.2022.11.15.05.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Nov 2022 05:31:24 -0800 (PST) From: Robert Foss <robert.foss@linaro.org> To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, quic_kalyant@quicinc.com, swboyd@chromium.org, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, vkoul@kernel.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek <jonathan@marek.ca>, vinod.koul@linaro.org, quic_jesszhan@quicinc.com, andersson@kernel.org Subject: [PATCH v2 06/12] drm/msm: Add support for SM8350 Date: Tue, 15 Nov 2022 14:30:59 +0100 Message-Id: <20221115133105.980877-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115133105.980877-1-robert.foss@linaro.org> References: <20221115133105.980877-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749569201121232831?= X-GMAIL-MSGID: =?utf-8?q?1749569201121232831?= |
Series |
Enable Display for SM8350
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Commit Message
Robert Foss
Nov. 15, 2022, 1:30 p.m. UTC
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 4 ++++
1 file changed, 4 insertions(+)
Comments
On 15/11/2022 14:30, Robert Foss wrote: > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > subsystem unit used on Qualcomm SM8350 platform. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index a2264fb517a1..39746b972cdd 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > /* UBWC_2_0 */ > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > break; > + case DPU_HW_VER_700: > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > + break; Shouldn't the second-last argument be 2 or 3 depending on DDR type? Konrad > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8350-mdss" }, > { .compatible = "qcom,sm8450-mdss" }, > {} > };
On Tue, 15 Nov 2022 at 14:42, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 15/11/2022 14:30, Robert Foss wrote: > > Add compatibles string, "qcom,sm8350-mdss", for the multimedia display > > subsystem unit used on Qualcomm SM8350 platform. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > --- > > drivers/gpu/drm/msm/msm_mdss.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > > index a2264fb517a1..39746b972cdd 100644 > > --- a/drivers/gpu/drm/msm/msm_mdss.c > > +++ b/drivers/gpu/drm/msm/msm_mdss.c > > @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > > /* UBWC_2_0 */ > > msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); > > break; > > + case DPU_HW_VER_700: > > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); > > + break; > Shouldn't the second-last argument be 2 or 3 depending on DDR type? Dmitry, can I get your input on this? I'm a little bit unsure of which dts properties some of these values are derived from. > > Konrad > > case DPU_HW_VER_720: > > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > > break; > > @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { > > { .compatible = "qcom,sc8180x-mdss" }, > > { .compatible = "qcom,sm8150-mdss" }, > > { .compatible = "qcom,sm8250-mdss" }, > > + { .compatible = "qcom,sm8350-mdss" }, > > { .compatible = "qcom,sm8450-mdss" }, > > {} > > };
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index a2264fb517a1..39746b972cdd 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) /* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; + case DPU_HW_VER_700: + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1); + break; case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; @@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8350-mdss" }, { .compatible = "qcom,sm8450-mdss" }, {} };