Message ID | 20231011-topic-sm8550-graphics-sspp-split-clk-v2-5-b219c945df53@linaro.org |
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State | New |
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Series |
drm/msm/dpu: correctly implement SSPP & WB Clock Control Split
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Commit Message
Neil Armstrong
Oct. 11, 2023, 11:59 a.m. UTC
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Comments
On Wed, 11 Oct 2023 at 14:59, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > Enable WB2 hardware block, enabling writeback support on this platform. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > index 4590a01c1252..d83a68a2cc0a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > @@ -321,6 +321,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = { > }, > }; > > +static const struct dpu_wb_cfg sm8550_wb[] = { > + { > + .name = "wb_2", .id = WB_2, > + .base = 0x65000, .len = 0x2c8, > + .features = WB_SM8250_MASK, > + .format_list = wb2_formats, > + .num_formats = ARRAY_SIZE(wb2_formats), > + .xin_id = 6, > + .vbif_idx = VBIF_RT, > + .maxlinewidth = 4096, > + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), > + }, > +}; > + > static const struct dpu_intf_cfg sm8550_intf[] = { > { > .name = "intf_0", .id = INTF_0, > @@ -418,6 +432,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { > .dsc = sm8550_dsc, > .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), > .merge_3d = sm8550_merge_3d, > + .wb_count = ARRAY_SIZE(sm8550_wb), > + .wb = sm8550_wb, > .intf_count = ARRAY_SIZE(sm8550_intf), > .intf = sm8550_intf, > .vbif_count = ARRAY_SIZE(sm8550_vbif), > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 4590a01c1252..d83a68a2cc0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -321,6 +321,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = { }, }; +static const struct dpu_wb_cfg sm8550_wb[] = { + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + static const struct dpu_intf_cfg sm8550_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -418,6 +432,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .dsc = sm8550_dsc, .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), .merge_3d = sm8550_merge_3d, + .wb_count = ARRAY_SIZE(sm8550_wb), + .wb = sm8550_wb, .intf_count = ARRAY_SIZE(sm8550_intf), .intf = sm8550_intf, .vbif_count = ARRAY_SIZE(sm8550_vbif),